Advances in semiconductor device technologies account for a large part of the growth in electronics. And there is no single event that summarizes the state of the electronic device art quite like the annual IEEE International Electronic Devices Meeting. Scheduled for December 6-8, 2010 at the Hilton San Francisco Union Square, the 2010 IEDM offers a variety of new developments in device and modeling technologies for RF/microwave designers seeking more accurate device models or higher-frequency integrated-circuit (IC) processes.

For example, K. Shinohara and coworkers from HRL Laboratories, working with A. Fung from NASA's Jet Propulsion Laboratory have developed gallium-nitride (GaN) double-heterojunction (DH) high-electron-mobility transistors (HEMTs) with 40-nm gate lengths capable of peak transition frequency (fT) of 220 GHz and peak maximum frequency of oscillation (fMAX) of 400 GHz. In work sponsored by the DARPA Microsystems Technology Office (MTO) NEXT program, the team applied vertical scaling in the AlN/GaN/AlGaN DH HEMT structure and reduction of access resistance through molecularbeam- epitaxy (MBE) regrowth of n+- GaN ohmic contacts to achieve excellent DC characteristics for passivated 40-nm-gate devices. According to the researchers, the measured fT and fMAX frequencies are the highest reported for a GaN HEMT.

Working with silicon germanium (SiGe) heterojunction-bipolar-transistor (HBT) technology, B. Heinemann and a team from IHP Microelectronics sought gains in fT and fMAX performance using the firm's 0.25-μm SG25H1 BiCMOS process technology. By scaling down the sizes of the emitter and collector widths from previous generations of the process, the researcher attempted to improve the high-speed performance of these SiGe HBT devices, and were able to achieve fT and fMAX frequencies of 300 GHz and 500 GHz, respectively, with minimum current-mode-logic (CML) ring oscillator delays of 2 ps.

Jeng-Wei Yu and team at the Institute of Photonics and Optoelectronics and Department of Electrical Engineering at the National Taiwan University reported on 100-GHz depletion-mode Ga2O3/GaN singlenanowire metal-oxide-semiconductor, field-effect-transistor (MOSFET) devices. Forming 60-nm devices by means of a photo-enhanced chemical oxidation method, the team fabricated singlenanowire MOSFETs with transconductance of 85 μS and cutoff frequency of 95 GHz. Photo-enhanced chemical (PEC) processing was used to form the MOSFET devices.

In pursuit of devices capable of operating into the Teraherz (THz) range, D. H. Kim and a research team at Teledyne Scientific Company demonstrated results for work on 50-nm, enhancementmode In0.7Ga0.3As pseudomorphic HEMTs (pHEMTs) with fMAX in excess of 1 THz while operating at a drainsource voltage (VDS) of 0.75 V. The pHEMTs were fabricated on 100-mm indium-phosphide (InP) substrates with a 10-nm-thick In0.7Ga0.3As channel, In0.52Al0.48As barriers, a 4-nm InP etch-stopping layer, and multilayer cap. The microwave performance was measured using a PNA series vector network analyzer (VNA) from Agilent Technologies using a standard line-reflect-reflectmatch (LRRM) calibration from 1 to 67 GHz. The transistor fT values were extrapolated (by extending the known values with a -20 dB/decade slope with a least-squares fit) as being 465 GHz for a 50-nm device with VDS of 0.75 V and 400 GHz with VDS of 0.5 V. A small-signal model was developed for extrapolating the values for fMAX, which were expected to be 1.08 THz at a VDS of 0.75 V. The researchers note that this is the highest value of fMAX ever reported for any FET with enhancement-mode operation.

Tae-Woo Kim, Dae-Hyun Kim, and Jesus A. del Alamo of Massachusetts Institute of Technology reported on 60-nm InGaAs HEMTs with self-aligned gates (SAGs) capable of excellent high-frequency characteristics as a result of low contact resistance as well as low source resistance. For devices with 60-nm gates, they report fT of 580 GHz and fMAX of 675 GHz with VDS of 0.6 V. They feel their results indicate a development path to FETs capable of fT and fMAX exceeding 1 THz.

Transistors, of course, will not be the only devices at the 2010 IEDM, as C. Y. Wen and researchers from the Department of Electrical and Computer Engineering at Carnegie Mellon University and the Data Storage Institute of Singapore explain their approach for reconfigurable RF inductors using vias that include phase-change materials with a difference in resistivity between amorphous (off) and crystalline (on) states. The measured inductance is1.9 nH in the off state with a peak quality factor (Q) of 12.4 at 1.9 GHz. The same device has inductance of 0.9 nH with peak Q of 5.8 at 5 GHz in the on state.

MAKING MODELS
Meanwhile, a great deal of work at IEDM 2010 will report on efforts to improve device models. For example, researchers at various IBM facilities teamed on a report covering large-signal substrate modeling of RF silicon-on-insulator (SOI) technologies, in particular for support of multiband, multimode wireless radios. The models were developed via harmonic measurements on a power amplifier (PA) using an impedance load-pull tuner.

Researchers from NXP Semiconductors focused on a surface-potential-based model for GaN HEMTs used in RF PAs. Existing GaN HEMT models are table based, while the new model uses a surface-potential equation to predict performance for changing device and substrate parameters. Comparisons to measurements of gate and drain currents and voltages and capacitances for various bias conditions show close agreement.

Finally, Chuan Xu and Kaustav Banerjee of the University of California at Santa Barbara , with Roberto Suaya of Mentor Graphics, offer details on modeling the electromagnetic (EM) coupling noise of through-silicon vias (TSVs) in three-dimensional ICs. Their models consider different active-layer scenarios, including those impacting bulk CMOS and SOI technologies.