The selection of technology greatly impacts the performance and functionality that can be expected from an integrated-circuit UHF RFID transponder.
Radio-frequency identification (RFID) transponder design techniques were introduced last month, in the opening installment of this two-part article series. This month more advanced methods will be explored for enhancing the performance of UHF RFID transponders, using four design examples in Germany, the United States, Italy, and Switzerland.
The German group was involved in pioneering work in UHF RFID, developing a variety of efficient circuit design techniques. However, their work required the use of a nonstandard 0.5-µm CMOS process. The US group proposed a low-cost design using Schottky diodes, employing novel data readout circuit and the capability of boosting the data rate to 10 Mb/s. The Italian group focused on low-power consumption and achieved submicrowatt power consumption with their digital module, based on AMI's 0.5-µm CMOS process. The Swiss group developed their UHF RFID transponder using silicon-on-sapphire (SOS) technology and achieved the farthest detection range.
Pioneering work was performed at Atmel (Heilbronn, Germany) in 2003.1 The RFID transponder chip was implemented with AMI's 0.5-µm dual-poly dual-metal silicon CMOS technology. The chip outperformed other reported RFID integrated circuits (ICs) by a factor of 3 in terms of required receive power level for a given base-station transmit power and tag antenna gain.
The German design group used a special CMOS fabrication process that contained Schottky contacts. The Schottky diodes are used in the rectifier structure, which is a five-stage Dickson charge pump. The resulting design delivered high saturation current (Is), low junction capacitance (Cj), and low parasitic capacitance (Csub). Since the input module consists of Schottky diodes, the chip features input impedance with quality factor (Q) as high as 30. The high Q increases the incident voltage level, a desirable trait for these UHF RFID transponders. The high Q is also supported by careful layout with low series resistance and low capacitances for on-chip interconnections and high-Q poly-poly capacitors. Their work also demonstrated that circuit performance could be improved by using a large aspect ratio and multifinger layout approach to minimize Rs. Their work did not mention the need for a voltage regulator.
Phase-shift-keying (PSK) modulation is employed in the reverse link (the modulator). Modulation is achieved by using an MOS varactor to change the input impedance between two states. The modulating reactance is achieved with the help of accumulation mode MOS varactor M1 and two poly-poly capacitors, C1 and C2 (Fig. 1). The capacitance of the MOS varactor is shifted from its maximum and minimum values by applying maximum and minimum voltage values to the varactor.
For control over the backscatter bandwidth, two driving inverters M4-M5 and M6-M7 are biased in the triode region, using biasing transistor M2 and M3 to control the current flow. The remaining four transistors, M8, M9, M10, and M11, form a buffer to drive logic signals coming from the digital block. The use of PSK leads to simultaneous higher power efficiency for DC power and high-modulated backscatter power.
The demodulator module is comprised of an envelope detector and pulse width demodulator (Fig. 2). The envelope detector uses the same structure as the rectifier, using a two-stage Dickson charge pump and smaller poly-poly capacitors. These capacitors together with the current sink determine the minimum gap width that can be detected by the circuit. The gaps between pulses are selected to be approximately 4 µs long, which is long enough to comply with stringent bandwidth regulation in Europe, but short enough to maintain continuity in a transponder power supply. The current sink serves as a large dynamic resistance, acting as a lowpass filter that limit the bandwidth and width of gaps detectable. The filtered RF envelope signal is then fed to a hysteresis comparator, which incorporates a Schmitt trigger to transform the RF envelope into digital high-low pulses. Incoming pulses are used for the system clock in the digital module and internal clock generation center, where each rising edge denotes the arrival of new bit. The integrator is then used to measure the length of the pulse, which is measured by a simple discriminator circuit to determine 1 and 0 data. Careful planning of protocol and control logic resulted in a power consumption of roughly 2.25 µW during normal operation, and 3.75 µW during write operation with a 1.5-V power supply.
Researchers at the University of Maryland developed a somewhat simpler design based on a rectifier and demodulator using Schottky diodes, similar to the work done by the German group. The Schottky contacts were fabricated " inhouse" using post-fabrication techniques employing focus ion beam (FIB) methods. The design also featured novel data readout circuitry that can boost data rates to 10 Mb/s. The transponder architecture is simple, designed for a read-only tag with no digital protocol and electronically erasable programmable readonly memory (EEPROM). 2 The RFID system is designed for half-duplex operation. The interrogating protocol uses Texas Instruments 134-kHz system protocols. The reader emits a continuous-wave (CW) signal to power up the tag. Once powered up, the transponder will transmit back its identification (ID) content via backscatterer. Since reader commands are not supported, a demodulator circuit is not needed.
A Dickson charge pump is used to construct the rectifier, with a stacked-diode architecture for the voltage regulator circuit. Seven Schottky diodes are stacked together to limit the DC output below 1.5 V. The regulator will not turn on if the generated voltage is lower than 1.5 V. The Schottky diodes are fabricated using a post-fabrication process with FIB. The design group has experienced successful Schottky fabrication with three different silicon CMOS processes, 1.5, 0.5, and 0.3 µm processes. 3
The RFID chip employs PSK backscatter. Similar to the Atmel design, a MS varactor diode is sandwiched between two capacitors and a set of cascaded inverters drives the varactor to two voltage extremes, changing its capacitance values between two distinct values in the process. Although the design is simple, it does not consider bandwidth implications, since its fast switching speed may exceed acceptable RFID receiver bandwidth limits at UHF.
The design group developed a novel data readout based on an inverter train circuit. The main function of the inverter train is to modify the delay between two inverters. The delay time of an inverter was intentionally increased to one-half of the pulse width of the oscillator output by changing the width and length ratio of the PMOS and NMOS structures in the inverters (Fig. 3). Devices D1 through D64 represent 64-b fixed data, which is already coded during the fabrication. All inputs are connected to switching NMOS devices, which are connected to on-or-off NMOS devices (M2, M4,...M128). FIB is used to implant Ga+ ions to permanently turn off some NMOS to create a permanent identification tag. The researchers' study shows that only 5.6 min is required to program a 200-mm wafer with 80,000 RFID chips. 4
When a 200-ns pulse, Vpulse, enters the circuit, the first switch (M1) is turned on and the first inverter (In1) begins to turn on. Inverter In2 begins to turn on at 100 ns. After 200 ns, inverter In2 is fully turned on, switch M1 is turned off, and switch M3 is turned on. The third inverter (In3) begins to operate at 200 ns. At 300 ns, inverter In2 and switch M3 are turned off and switch M5 is turned on. The single pulse will reach the last inverter (IN128) and turn on switch M127. After turning off the last switch (M127), the pulse vanishes. Voltage Vpulse is generated using a modified ring oscillator. An additional capacitor is inserted between the first and second inverters to modify the pulse width to a value of 200 ns. The periodic pulse will repeat the output data pattern with the same period as that of the ring oscillator.
The design group noted that successful fabrication of Schottky contacts is not guaranteed in a CMOS process, and post-processing will be needed in most cases. Successful Schottky device fabrication has been reported on non-salicided CMOS processes, but not on salicided CMOS processes without special modifications in the processing steps. Therefore, it is essential to find other efficient ways to fabricate RFID transponders without using Schottky contacts.
An alternative to using silicon CMOS is silicon BiCMOS, as demonstrated by researchers at the University of Pisa. They had implemented UHF and microwave passive RFID transponders using AMI's 0.35-µm BiCMOS process. 5
The rectifier was designed using a PN diode rather than a Schottky-charge-pump approach. This method converts RF voltage into two DC voltages of 0.63 V (VDDlow) and 1.35 V (VDDhigh). A one-stage multiplier supplies VDDlow to the digital section and the modulator, while a two-stage multiplier supplies VDDhigh to power up the voltage regulator. This choice of rectifier design was made to optimize the AC-DC conversion efficiency.
The time constant of the coupling capacitance in the rectifier/envelope detector circuit is set to be much larger than the pulse-low interval of the pulse-width-modulated (PWM) signal, which is about 2 µs. This ensures low ripple when the transponder receives data. However, the Q factor is high (reaching 45), which places great demand on the antenna design and also the need to guard against diode breakdown. Although the diode works safely under Europe's 0.5-W EIRP limit, prolonged operation in environments allowing higher operating-levels is not guaranteed.
The modulator uses PSK backscatter to transmit data to the reader. In this design, the capacitance variation of switch M1 (an MOS varactor) in saturation and cut-off modes is exploited. Once the modulation depth is chosen, the dimensions of M1 are fixed. Device M2 is used to allow the user to set the output resistance, which is made very large so the impedance seen from the matching network is negligible compared to the antenna resistance. Switch M2 is sized for minimum dimensions to ensure low resistance of a few kilo-ohms. For a variation in output capacitance of about 350 fF, M1 has width and length of 670 and 0.35 µm, respectively. A capacitor, CIN, with value of 650 fF is inserted between the driving buffer and varactor to limit the channel bandwidth.
The demodulator reuses the onestage rectifier topology, which becomes an envelope detector. A lowpass filter after the envelope detector is formed using the inverter's input capacitance and the drain-source resistance of an NMOS device. The NMOS device is driven by VDDlow to obtain a variable resistance. When the input power increases, the voltage output at the envelope detector output will increase and time constant would be too low to follow the signal variation. As the NMOS gate (driven by VDDlow) increases at the same time, the time constant is reduced, thus ensuring the correct operation of the demodulator.
This design group made a significant contribution in the design of a lowpower digital module. It employs a generic 6502 compatible processor with 65 kb of addressable memory that is clocked at 1 MHz. The group has shown that it is possible to implement a processor-based RFID digital section with power consumption below 1 µW. The key is to use CMOS and pseudo-NMOS logic schemes, which are operating in the sub-threshold region with a power supply of 0.6 V. The use of the additional processor offers much flexibility, including reduced design time and an easy protocol upgrade path.
Researchers from the Swiss Federal Institute of Technology proposed an effective RFID structure using SOS technology. 7 The technology offers low-threshold-voltage CMOS as an alternative to Schottky diodes. The technology's highly isolated devices exhibit low parasitic capacitance compared to bulk CMOS processes. The power consumption is also generally lower than bulk CMOS, further improving the RFID reading range due to low device and interconnection capacitances. On the negative side, SOS is not yet a commonplace technology, very vendor specific and about 10 percent higher in die cost than bulk CMOS devices.
The rectifier module is made of a three-stage, full-wave voltage-doubler cascade, which is analogous to the Dickson charge pump. The rectifying devices are diode-connected SOS transistors with low threshold voltage, low reverse current, and low parasitic capacitance; similar to Schottky devices. Negative-wave rectification is designed using a fully depleted SOS technology. This yields higher rectifier efficiency at the cost of requiring a differential structure for the other blocks. To prevent voltage overdrive when the transponder is working at close proximities, a limiter was added at the output of the rectifier. A resistive-capacitive (RC) controller loop shorts the output when the middle voltage exceeds threshold voltage. The design has a shortcoming of high current consumption when the transponder is in close proximity to the reader, which in turn reduces the input impedance of the transponder as seen by the antenna, reducing the modulation depth.
This research team used ASK backscatter-rather than PSK. The thinking was that ASK could be used with equivalent power consumption as PSK, provided that one of the states is active most of the time (a low duty cycle). The use of ASK was also supported by a protocol designed to embed data in either the presence or absence of a backscattered signal. For a data "1," the ASK modulator toggles at the speed of its internal intermediate-frequency (IF) oscillator. For a data "0," the ASK modulator is switched off and the reader must be able to detect the lack of the backscattered signal. The ASK approach allows the modulator circuit to be implemented with a simple MOS switch since it is independent of frequency, with no reactive element compared to the PSK modulator (Fig. 4). The ASK modulator also allows greater freedom in the choice of antenna, since the matching requirement is not a major consideration.
The demodulator consists of envelope detector network and an averaging filter (Fig. 5). Diodes in the envelope detector are realized using low threshold voltage diode-connected transistors. Signals Venv and Vref are the envelope and rectified average of the received signals, respectively.
Signal Venv clocks the transponder while signal Signals Vref provides the voltage reference for comparison in the decoding process. When the RF input signal (RFIn) rises, capacitor Ca charges with the RF envelope. When RFIn falls, capacitor Ca discharges through resistor Ra due to the inverse current of the diode. The components values have been sized for a time constant that is within a few nanoseconds of the operating signals in order to follow the RF envelope (Venv) of those signals.
The diode leakage current is set high enough so that discharge will occur rapidly at Ca. Capacitor Cc and its associated diode provide the voltage reference, Vref. The diodes in series form a voltage divider. When RFIn rises, Cc charges down to one-half the amplitude of the envelope signal. When RFIn falls, the charged voltage of Cc will slowly decay due to the inverse current of the parallel diode. The data slicer handles regeneration of the data signals. The Gn signal is tied to negative voltage (V-) during the addressing mode. When the envelope voltage (Venv) is higher than the reference voltage (Vref), CK1 rises to V+ and D-FF toggles since it is positive edge sensitive. Decided signals Datain and #Datain are then fed into the digital control circuitry for processing.
The design's digital block is hardwired. The prototype transponder contains a 2-b ID only. It toggles between three states: power up, addressing, and reading modes. As a result, its state machines are considerably simple than commercial RFID transponders based on the Gen2 protocol. Due to its asynchronous logic scheme and simple digital protocol, this design has minimal power consumption at the expense of minimal functionality.
This review of four RFID transponder design approaches shows how technology selection for both analog and digital modules greatly impacts performance. Analog modules can be implements with non-standard CMOS or BiCMOS, while digital modules can be hardwired or programmable. The tradeoffs in different approaches include power consumption, interrogation range, and functionality.
REFERENCES
