The OpenVPX/VITA 65 high-speed bus standard is helping embedding computing vendors work together to integrate many different board- and card-level products and interfaces into reliable solutions.
VME is one of the oldest commercial off-the-shelf (COTS) buses still being designed into new military systems. At one time, it offered the industry's fastest backplane bus. Its 320-MB/s speed was impressive when the format was first introduced in 1997. But today, the parallel VME bus has been superseded by high-speed serial interfaces like Serial RapidIO and Gigabit Ethernet. For military systems designers, high-speed bus options are many, but the Open VPX/ VITA 65 standard o ffers a way of achieving compatibility among these many interfaces.
VITA, the standards group that manages VME technology, started with VME (VITA-1.0). VME320, or VME 2eSST, is de fined by VITA 1.5. The high-speed serial platforms include VPX (Table 1), VXS (Table 2). and XMC (Table 3). VPX and VXS are board standards like VME and use 3U and 6U form factors. XMC is a mezzanine card standard using high-speed serial interfaces; it is an alternative to PCI mezzanine card (PMC) products based on the use of a parallel PCI interface.
VME and PMC with its PCI bus are relatively stable. The high-speed serial interfaces are well de fined but the number of options available can be mind numbing. The list includes serial interfaces such as Serial RapidIO, In finiBand, PCI Express, Gigabit Ethernet, 10 Gbit Ethernet, Aurora, HyperTransport, and XAUI. Although these are all point-to-point connections, they typically work with a hub or switch.
In addition, the reduction of pins needed to deliver comparable throughput on a high-speed serial interface is significantly lower than a parallel interface like VME or PCI. This allows many boards and platforms to handle multiple connections. A single connection allows a star configuration while dual connections provide support for a dual star providing redundancy (Fig. 1). A full mesh requires more connections but provides maximum bandwidth. A dual mesh provides redundancy but it is also a very complex backplane. Even tree or inverted-tree architectures and asymmetrical designs are options that may be more suitable to some applications. For example, a radar-processing system might work best with an inverted tree where many inputs are reduced to a single result with each level of the tree handing o a smaller, processed subset of data to the next level.
The options get even more complex when mixing interconnects. This complexity is compounded by the more advanced MultiGig connectors used with VXS and VPX high-speed serial interfaces like those from Tyco Electronics that are actually multiple wafer-size circuit boards themselves (Fig. 2). These are used on VXS and VPX boards like the 6U VPX Champ-AV6 (Fig. 3) from Curtiss-Wright Controls Embedded Computing with four dual-core microprocessors from Freescale Semiconductor with built-in Serial RapidIO connections. Add to this the ability to mix and match high-speed serial interfaces, typically Ethernet with another interface, and it is easy to see how the number of options grows significantly. Designers employing VXS and VPX o en require custom backplanes taking advantage of the backplane input/output (I/O) connectors available on the 3U and 6U boards further adding to the chaos. Attaining a level of compatibility between vendors was more than a challenge. OpenVPX looks to bring a little order to the chaotic number of options.
OpenVPX, now VITA 65, is a systems-level specification designed for seamless operation between boards and systems. It does this by pro ling a useful subset of the available standards such as those from VITA. System designers can then start with a pro file instead of a lower level form factor and interconnect level. It came about through ideas and cooperation from board vendors such as Mercury Computer Systems, Curtiss-Wright Controls Embedded Computing (CWCEC), GE, and Tek Microsystems, as well customers like Boeing so designs would not be so unique that second sourcing and upgrades would be out of the question. This was often the case where designs could utilize the host of options not to mention the customization of the I/O connections.
Some of the considerations that went into VITA 65 include backplane architectures and development chassis interconnect topologies, module level pin designations and protocol definitions, power and system signals as well as interoperability compliance issues. It also defines various size pipes used for the serial interfaces as well as multiple logical planes for utility, management, control and data. Planes de fine logical and physical interconnects. Pipe definitions include an Ultra Thin Pipe (UTP), a Thin Pipe (TP), a Fat Pipe (FP), a Double Fat Pipe (DFP), a Quad Fat Pipe (QFP), and an Octal Fat Pipe (OFP). This matches well to most high-speed serial interfaces. Interface speeds up t o 6 . 2 5 Gb/s per signal pair are supported.
VITA 65 takes a pragmatic approach to design. It chooses certain options, possibly at the expense of others, to de fine how an OpenVPX system will work. This should guarantee that every single OpenVPX board will plug into an OpenVPX backplane and work.
OpenVPX has turned into a broad cooperative effort. It did not start out that way and there were a few heated discussions along the way. There were a few NDAs and possibly a few arrows exchanged. The resulting OpenVPX Working Group, that has since dissolved, and the standard is better for the effort that is now under VITA. The standard is based on VITA 46/VPX and VITA 48/REDI specifications adding aspects such as air-cooled interoperability with Rear Transition Modules (RTMs). This allows vendors to design boards that are interoperable with the competition. Customization will still be available and will differentiate platforms.
Designers can now select from a set of limited parameters such as form factor (3U or 6U), interconnect topology and the number of slots in the backplane. For example, Elma Bustronic's 7-slot OpenVPX Hybrid backplane (Fig. 4) has five VPX sockets interconnected using a full mesh with four serial interfaces per board. This eliminates the need for a switch. It also has a pair of VME/64x slots as well with the VME bus routed to the VPX connectors. The backplane references the BKP6- DIS05-11.2.16-1 profile. Assembly and deployment is now significantly easier when the backplane and boards used with the system are VITA 65 compliant.
The basic set of profiles allows designers and vendors to work with new compatible hardware but the base set is only the starting point. There will not be a flood of new designs but will be added as needed or as new architecture combinations become more popular. Two of the new VITA specifications that will have an impact are VITA 66 (Fiber Optic Interconnect) and VITA 67 (coax Analog/RF Interconnect). Fiber and coax connections are common on the front panel but more connections are likely to move to the rear as these standards come into play on the boards and backplanes. This is where VITA 65 support will be critical. As Ray Alderman, VITA Executive Director, says, "OpenVPX: It's all about the backplane." In one sense, VITA 65 has brought back the commonality that VME had delivered in the past.
The military market is unlike consumer and commercial markets where technology turnover is often measured in months. The lifetimes of many military systems are measured in decades. This is one reason that parallel bus-based solutions like VME, CompactPCI, and even PC/104 are still found in new military designs. These typically target the large military and aerospace replacement and upgrade market.
VXS attempts to bridge the gap between a full high-speed serial backplane like VPX and the parallel interface of VME. The challenge in the replacement and upgrade market is whether the backplane can be changed. If not, VXS boards still work but their serial interface is wasted. Otherwise, designs open up a world of options.