Modular signal-processing solutions provide a great deal of exibility in both military and industrial applications. By swapping modules or cards in a mainframe, the character of a system can be quickly changed, and performance capabilities rapidly modi fied to suit an application. A number of standards have been established to improve the compatibility of signal-processing modules, including the Peripheral Component Interconnect (PCI) standard and the PCI mezzanine card (PMC) housing format, to ensure that modules from one manufacturer will t in standard mainframes and work seamlessly with modules from another manufacturer. In terms of the performance and capability available from such PMC modules, New Jersey-based Pentek (www.pentek.com) has leveraged the flexibility and power of field-programmable-gate-array (FPGA) components in its PMC designs to create software-de fined radios (SDRs) and high-resolution analog-to-digital converters (ADCs) that are well suited to the demanding requirements of military and aerospace applications.
PMC modules are widely supported and widely used in ruggedized military applications, ideal for their small size and durability but also for their high performance levels. The popular mezzanine card standard has enjoyed performance enhancements in recent years, by way of modi cations and add-ons to the original electrical and mechanical standards. For example, the VITA 42 standards is a relatively new de nition for high-speed serial links to mezzanine boards for embedded communications standards. Also known as XMC(1), this extension to the basic set of PMC requirements de nes two connectors that join the mezzanine board to the host or carrier board. A dual connector XMC interface supports serial bit rates of 3.125 GHz and data rates of 5 GB/s in each direction.
Pentek's latest PMC designs make full use of the standard's capabilities, in the form of the rm's new model 7150 high-speed quad data converter, model 7151 high-speed SDR module, and model 7152 highspeed SDR with 32-channel digital downconverter (DDC). All three PMC modules make good use of the processing power of Virtex-5 FPGAs from Xilinx (www.xilinx.com), which support fast processing speeds as well as programmable exibility.
A great deal of digital signal processing (DSP) is needed in most modern communications systems because of the complexity of current modulation and demodulation schemes, encoding and decoding techniques, protocol handling, and encryption and decryption methods. By incorporating FPGAs for a multitude of DSP functions, traditional DSP boards can be eliminated from a PMC design, shaving the number of boards required in a PMC module. In a modern communications system, front-end FPGA processing can also extract signal information before it leaves a PMC module, to lessen the need for downstream processing and result in lower downstream data rates. The flexible programmability of FPGAs also allows them to readily support new functions and standards without redesigning the hardware module.
Pentek's model 7150 high-speed data converter (see figure) packs four 200-MHz 16-b ADCs and a pair of Virtex-5 FPGAs into a single PMC/ XMC module. It connects directly to the radio-frequency (RF) or intermediatefrequency (IF) ports of a communications system to digitize signals with high resolution and provide the capability to detect extremely small signals across wide bandwidths.
According to Rodger Hosking, Pentek Vice-President, "The boost in sampling rate to 200 MHz means that users will be able to directly digitize nearly 100 MHz of bandwidthinvaluable for engineers working on wideband radar and wideband communication systems. The innovative design of the 7150 assigns strategic functions to both Virtex-5 FPGAs for optimum performance. One is dedicated to interface connectivity and the other toward real-time signal processing, and both FPGAs are available in different sizes and types. As a result, the 7150 makes an ideal platform for adding custom IP cores to provide outstanding overall system performance over a wide range of applications."
Using a pair of FPGAs and essentially partitioning their functions results in improved overall operating efficiency for the 7150 PMC module. The FPGA devoted to real-time signal processing handles data flow and data routing, controls all clock and synchronization functions, and manages memory resources. Because it is at the center of all data flow paths, it is well positioned for performing data processing and DSP functions within the PMC. The other FPGA, devoted to interface connectivity, is responsible for providing the PMC's system connectivity through a PCI-X or optional PCIe interface. Dedicating these functions to the second FPGA frees the first FPGA to operate as a high-speed DSP. It should be noted that, because Xilinx maintains a consistent pin configuration among its various Virtex-5 family of FPGAs, different Virtex-5 models can be used to achieve various performance levels within a 7150 PMC, depending upon the needs of an application. For example, Virtex-5 LXT devices may be the optimum choice for demanding logic requirements, while SXT devices may best satisfy DSPintensive applications.
The main signal-processing FPGA is supported by three banks of DDR2 Synchronous dynamic random-access memory (DRAM), doubling the amount of memory in previous designs to a total of 1.5 GB. This enables real-time capture of 2.56 s of signal data sampled at 200 MHz, which is ideal for use in wideband radar systems. The DDR2 SDRAM acts as a large elastic buffer, capturing data in real time and delivering it at a slower aggregate rate through the module interfaces. Built-in triggering modes allow capture of a wide range of block sizes, while DMA controllers simplify data transfers to the PCI-X bus.
The 7150 PMC module retains a front-panel synchronization bus from the firm's earlier VME/PMC module designs. The bus allows multiple boards to be easily synchronized via a multipin ribbon cable to create larger multichannel systems. Synchronization signals include reset, gates, pulse per second (PPS), sync and clock signals. In addition to the sync bus, the sampling clock can be fed from an onboard crystal oscillator or through a front-panel external clock input connector.
Because it meets PMC/XMC standard requirements, the 7150 data converter can mount on VME/VXS host boards. In addition, the module can be supplied in other form factors, such as PCI and PCIe boards for use in desktop computers and blade servers, and 3U and 6U compact PCI. The 7150 will be shipped initially with a PCI-X interface, and available with a PCIe. The PMC module is supported under the Linux, Windows and VxWorks operating systems, with board support packages for each operating system. A board support package includes an operating system driver as well as a full-featured ReadyFlow C language library to support all board functions and provide sample applications for quick development startup.
Defining Radio Performance
In terms of density, model 7151 SDR may be even more impressive than the model 7150. It combines four 16-b, 200-MHz ADCs with a Virtex-5 FPGA for DDC functionality, achieving 256 DDC channels that are independently tunable across four 100-MHz bands in support of the ADCs. Again, all of this performance and capability fits within a single-slot PMC module. Compared to hardware downconversion solutions, it provides a dramatic reduction in cost per downconverted channel. The software radio allows an operator to apply four RF or IF input signal streams to bandwidths as wide as 100 MHz and digitize them at 200 MHz with 16-b resolution. For military applications, the SDR module is ideal for signalintelligence applications. In commercial communications, it is well suited for GSM cellular-telephone monitoring.
The 7151 accepts input signals to +10 dBm on front-panel, 50-ohm SMC connectors. The input connectors are transformer coupled to the four 200-MHz ADCs. Digitized signals are sent to the Virtex-5 FPGA for routing, formating, and DDC signal-processing operations. Model 7151 can downconvert any signal within any of its four digitized 100-MHz input bands. Downconverted information is arranged in four banks of 64 DDC channels. Each bank can be configured for a unique output signal bandwidth to accommodate applications requiring mixed signal types or multiple modulation schemes. Each DDC bank can be independently sourced from any one of the four ADCs, which are typically assigned to specific antennas. Four independently controllable input multiplexers select one of the four ADCs as the input source for each DDC bank. In this way, many different configurations can be achieved, including one ADC driving all 256 DDC channels and each of the four ADCs driving its own DDC bank. Each of the 256 DDCs has an independent 31-b tuning frequency setting that ranges from DC to one-half of the sampling frequency. This flexibility allows the model 7151 SDR to simultaneously capture hundreds of signals across different modulation types, bandwidths, and antennas.
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As Rodger Hosking notes, "With its highly optimized 256-channel DDC IP core engine, the model 7151 represents an entire software radio front end, boasting a channel density eight times higher than any other competing product in the marketplace. The Model 7151 is fully supported with drivers and it comes ready to use with the FPGA code already developed and installed. Not only does the 7151 module reduce development time and risks, it also saves designers space, power and costs in their software radio systems. Plus, the flexible decimation settings, input selections and tuning options, all unique to the Model 7151, provide engineers with unprecedented choices to suit specific applications.
All 64 channels within a DDC bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156 kHz to 1.25 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-b coefficients. Rejection of adjacent-channel signal components within a selected passband is better than 100 dB. Each DDC provides a complex output signal stream of 24-b in-phase (I) and quadrature (Q) samples. The 7151 SDR can be attached to any PMC carrier board. It is also available as model 7651, as a PCI board version, for use in a desktop computer. The SDR is supported by software packages for Linux, Windows, and VxWorks operating systems.
Of course, in terms of density, model 7152 yields nothing to its PMC counterparts. It melds four 200-MHz 16-b ADCs with 32 DDC channels made possible by the on-board Virtex-5 FPGA. While it lacks the total number of DDC channels in the 7151, the 7152 SDR solution adds power measurement capability to each of its 32 DDC channels. In addition, each channel incorporates a threshold detector which will send an interrupt to the system processor if the average power level of any DDC channel falls below a programmed threshold value. The built-in power meters and threshold detectors offload these tasks from a downstream processor. Also, each DDC channel offers programmable gain and phase adjustments, which can be applied individually or synchronously to all 32 channels, to execute beamforming functions. As with the other modules, the model 7152 is also available in a PCI board format, as model 7652. It is supported by software running under the Linux, Windows, and VxWorks operating systems.
For those who do not require the extreme high performance of these newer PMC modules, but would prefer the compactness and versatility of the PMC/XMC form factor, the firm offers an extensive line of additional PMC modules, including the models 7141-703 dual digital upconverter/downconverter and the model 7141 four-channel ADC. The model 7141-703 dual digital upconverter/ downconverter features a pair of 14-b, 125-MHz ADCs and a pair of 16-b, 500-MHz DACs in a VITA 42.0 XMC compatible PMC module. The software radio transceiver is capable of handling bandwidths to 40 MHz and more. The front end accepts two fullscale high-frequency (HF) or IF signals to +10 dBm on front-panel 50-ohm SSMCX connectors with transformer coupling into the 125-MHz ADCs. The data converters send digital outputs to a Virtex-II Pro FPGA for signal processing or for routing to other modules. The module's digital downconverter stage is based on a Texas Instruments/Graychip model GC4016 quad digital downconverter chip that accepts four 14-b inputs or three 16-b digital inputs from the FPGA. Each channel of the GC4016 can be set for independent tuning frequency and bandwidth. The output bandwidth for each channel can be selected from 5 kHz to 2.5 MHz, or channels can be combined to reach a bandwidth of 10 MHz. For upconversion purposes, the 7141-703 uses a TI DAC5686 digital upconverter chip.
The model 7142 four-channel ADC with single-channel DAC is also a software radio interface solution that is compatible to the VITA 42.0 XMC standard. It features four 125-MHz 14-b ADCs, a 500-MHz 16-b DAC, and a pair of FPGAs. It also contains 768 MB of DDR2 SDRAM memory. The model 7142 accepts fou full-scale analog HF or IF input signals to +10 dBm using four LTC2255 14-b 125-MHz ADCs from Linear Technology (www.linear.com). The ADCs send their digital outputs to a Virtex-4 FPGA for signal processing or for routing to other modules.
The model 7142 employs a TI DAC5686 digital upconverter chip that works with baseband or complex data from the FPGA at signal bandwidths to 40 MHz. The upconverter can interpolate and translate real or complex baseband signals to any IF center frequency between DC and 160 MHz. It can also deliver real or quadrature analog outputs to 320 MHz to the 16-b DAC. Analog output signals are available through a 50-ohm MMCX connector. The model 7142 transceiver can provide as much as 2 s of delay or data capture at 125 MHz. Pentek, Inc.; One Park Way, Upper Saddle River, NJ 07458; (201) 818-5900; Fax: (201) 818-5904; E-mail: firstname.lastname@example.org; Internet: www.pentek.com.