Dielectric-resonator oscillators (DROs) provide low-noise signals for a variety of wireless and other applications. Computer- aided-engineering (CAE) tools can be invaluable in designing and optimizing the performance of these oscillators, as will be shown with the design for a prototype oscillator in support of wireless-localarea- network (WLAN) applications at 5.5 GHz. By applying a number of different CAE tools, including a harmonic-balance simulator as well as linear and nonlinear models, a prototype was developed with low phase noise, high output power, and low harmonic content.
The performance of DROs has been limited for some time by the poor quality of ceramic materials. But with the advanced development of improved dielectric materials, and the growth of requirements in cellular communications and satellite communications (satcom) systems, it is possible to produce DROs with excellent spectral purity.
Microwave oscillators form an important part of many microwave systems, including in radar, communication links, navigation, and electronic warfare (EW) systems.1 With the rapid advancement of technology there has been an increasing need for better oscillator performance in support of more complex modulation formats. Emphasis has been on low noise, small size, low cost, high efficiency, high temperature stability, and reliability. DROs represent an interesting solution as a quality oscillator for fixed frequency or narrowband tunable oscillators.2 Moreover, with the advent of temperature-stable materials, the DRO has emerged as a high quality factor (Qs of typically 9000 at 10 GHz), low loss, low-temperaturecoefficient (typically 6 ppm/C), and conveniently sized element for microwave integrated circuits (MICs) as well as in discrete circuit designs.
DRs are available in different configurations. Disc or puck-shaped DRs are most frequently used in microwave circuits since they can be easily manufactured. Furthermore, the discs are mostly operated in the transverse electromagnetic TE01d mode, which represents the lowest possible resonance- mode frequency. Recalling, the dielectric geometry and immediate surroundings, this resonance frequency can be calculated to an accuracy of about 1 percent or less.
The ultimate aim of the present work is to produce a free-running DRO operating at 5.5 GHz for WLAN applications. Compared to the authors' previous work of developing a DRO for use at 3.65 GHz,3 the effects of cavity walls on the prediction of resonance frequency are included here. The present work starts with the activation of the dielectric resonator at its TE01d resonance mode, and then the required instability region of the low-noise active device. The oscillation conditions and design of DRO were based on using two-port scattering parameters (S-parameters), then stability and the tenability of the DRO were examined, followed by the measurement of DRO characteristics. Several CAD tools such as the Advanced Design System (ADS) software from Agilent Technologies,4 Computer Aided Resonator Design (CARD)5 from Krell Engineering, Dr. Rez Design Software,6 and Temax software were used.
The practical model of the DR coupled to a microstrip line inside a cavity enclosure with tuning screw was modeled using Dr. Rez software. The results were also verified by the other software tools to optimize the reasonable coupling coefficient and Q factor of the DR at a 5.5-GHz operating frequency. The DR is a type D88 provided by Morgan Electro Ceramics, and has a diameter (Dr) of 7.05 mm, length (Lr) of 2.65 mm, frequency range of 5.462 GHz 200 MHz, temperature coefficient of tf = 5.4 ppm/C, dielectric constant of 88, and minimum unloaded Q of 6000.
The DR is modeled as a parallel resonant circuit where the values of inductance (L), capacitance (C), and resistance (R) are adjusted to provide the proper resonant frequency of 5.5 GHz and a high Q factor. The DR and the 50- microstrip line are mounted on RT/Duroid 5870 substrate material from Rogers Corp. with dielectric constant, er , of 2.33, thickness, T, of 0.79 mm, and tan d = 0.0012. The performance of both and Q of the DR were also optimized for two different types of spacers (to adjust the height of the DR on the substrate). The first has a height of 0.79 mm and er =2.33, the second spacer has a height of 1.5 mm and er = 2.55. A low-dielectric-constant spacer was used so that it does not become an electric extension of the dielectric resonator. However, it was found that the best distance between the DR and microstrip line was 6.5 mm with a 1.5-mm spacer. The simulated position of the resonator relative to the line to which it couples was found to be approximately a quarter wavelength for the 1.5-mm high spacer for reasonable values of QL = 1962 and = 2.96. The equivalent element values of simulated DR coupled to the microstrip are given in the table.
After DR modeling was performed, an active device was selected. A model ATF-35143 pseudomorphic high-electron- mobility-transistor (PHEMT) device from Avago Technologies was chosen to meet the requirements of the design. The linear model at the drain-source-voltage operating point of Vds = 3 V and Ids = 30 mA was verified using the ADS simulation package, revealing a stability factor of 0.8671 at 5.5 GHz. Thus, positive feedback was employed through an open stub at the source of the transistor to improve the instability region inside the Smith chart at 5.5 GHz. Figure 1 shows S11 and S22 for the linear model of the active device with positive feedback. The maximum values of input and output reflections are 6.04 and 4.43 at 5.5 GHz, respectively, adequate to establish the oscillation condition based on negative resistance.
An initial linear simulation for the DRO was carried out to determine the output-matching network and to predict the expected oscillation frequency. Figure 2 shows the linear model of the DRO used for the simulation. After achieving satisfactory results from the linear model, a nonlinear model was substituted to optimize phase-noise performance and output power. Figure 3 shows the nonlinear DRO model. After optimization, a prototype board was constructed (Fig. 4) and measurements carried out.
After slight adjustment of DR position, the free-running frequency was measured as 5.49981 GHz, a 0.0034 percent relative error compared to the target frequency. The measured output power was +14.17 dBm and this agrees very well with the nonlinear model. A tuning range of 105 MHz was achieved without degrading the output power (a minimum of +12 dBm) or phase-noise performance. Figure 5 shows the output spectrum of the free-running DRO. Frequency pulling and the external quality factor were 300 kHz and 763, respectively. The frequency pushing for a maximum of 1 V was 25 kHz and this effect on output power was very low. The phase noise offset 10 and 100 kHz from the carrier was -103 and -123 dBc/Hz, respectively. The simulated and measured harmonic rejection levels were -32 and -28 dBc, respectively. The measured efficiency of the DRO was 13.4 percent.
1. Darko Kajfez and P. Guillon, Dielectric resonators, 2nd ed., Noble Publishing, Stone Mountain, GA, 1998.
2. M. Regis, O. Llopis, and J. Graffeuil, "Nonlinear modeling and design of bipolar transistors ultra-low phasenoise dielectric-resonator oscillators," IEEE Transactions on Microwave Theory and Techniques, Vol. 46, No. 10, October 1998, pp. 15891593.
3. R. A. Abd-Alhameed, M. Zewani, N. T. Ali, P. S. Excell, J. G. Gardiner, and N. J. McEwan, "Simulation and measurement of a C-band low-noise dielectric resonator oscillator," Microwave Journal, Vol. 47, No. 4, April 2004, pp. 64-78.
4. Agilent Technologies, Advanced Design System, Version 2003C, www.agilent.com.
5. Trans-Tech., "Introduction to Dielectric Resonators," Notes numbers 1030, 851, and 821, Web site: www.trans-techinc.com/TTapnote.cfm
6. ComNav Engineering, Dr. Rez Design Software, www.comnav-eng.com/index.html.