When a multiport analyzer is not available, S-parameter measurements can be made on differential devices using a low-cost, two-port vector network analyzer.
Differential (balanced) topologies are very often used in RF and microwave circuits, and particularly in integrated circuits (ICs), such as MMICs and single-chip receivers. Such circuits are usually impedance matched at the input at a single carrier or local-oscillator (LO) frequency. Unfortunately, manufacturers' data sheets do not always provide the required differential input impedance of the device at the frequency of interest. In such a case, it is necessary to characterize the differential input admittance or impedance of the balanced device prior to impedance matching. Because low-cost commercial vector network analyzers (VNAs) for measuring scattering (S) parameters generally are equipped with two single-ended test ports, an effective approach is needed for characterizing differential devices with a two-port VNA.
Three methods are often considered for solving this problem:
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Among these three methods, the third one is certainly the most powerful. Nevertheless, for the design engineer only occasionally confronted with the characterization of differential input impedance of balanced devices in narrowband RF applications, a multiport test system provides unneeded measurement capability and cost.
For such cases, it is possible to use a less-expensive solution based on a two-port VNA (model HP8753D from Agilent), a few additional components, and the classical approach for characterizing a differential amplifier.4 This low-cost solution requires only one port of the VNA with the capability of displaying S11 or S22 parameters on the admittance Smith Chart. This method was originally developed for measuring the differential input impedance of the mixer's balanced RF input port on the model UAA2080T single-chip pager receiver manufactured by Philips Semiconductors.6 Measurement accuracy was critical in this case, since it impacted both the output power matching of the LNA stage and the 90-deg. relative phase difference between the receiver's in-phase (I) and quadrature (Q) channels. The differential input impedance of the mixer's balanced RF ports was successfully performed at 40.68 and 224 MHz for two different applications. Only the lower-frequency example will be covered here.
According to the Philips Semiconductors applications handbook,6 the UAA2080T integrates a mixer in each I and Q channel. The electrical diagram of one of these mixers is reproduced in Fig. 1: a classical double-balanced Gilbert multiplier, operating with balanced drives at the RF and LO ports. Due to the symmetry, these inputs can be characterized by the representation currently used for modelling the input circuit of a differential amplifier.4 The most classical equivalent input circuit of a differential amplifier, is the π, (or Δ) input network shown in Fig. 2. To further simplify the calculations, it is wise to consider the admittances of the three elements in Fig. 2. These admittances include Yic = Yn + Yp which is the common-mode input admittance. For a well-balanced device such as the mixer in Fig. 1, Yn ≈ Yp = Yc, and consequently:
where:
Yd = the differential input admittance, when Yc = 0.
Referring to Fig. 2, in the general case (when Yc ≠ 0), the differential input admittance that must be considered for performing a balanced impedance matching is:
A single-ended VNA cannot measure Yid directly; nevertheless, an indirect measurement method enables such an instrument to be used. This method consists in first determining the admittances Yd and Yc with the two-step measurement process that follows. In the first step, port 1 of the VNA is AC connected to the two differential inputs (Fig. 3). The resultant S11 parameter yields the common mode input admittance Yic:
and consequently,
where:
Y0 = 20 × 10-3 O-1 is both the output admittance of the VNA and the characteristic admittance of the transmission lines between the VNA's output and the calibration plane.
In the second step, port 1 of the VNA is connected to one differential input, while the second is AC short circuited to ground (Fig. 4). The resultant S11 parameter yields Yis:
and consequently:
Expressions 4 and 6 give the values of the elements in Fig. 2:
After substitution of Eqs. 7 and 8 into Eq. 2, the final expression of the differential input admittance can be found as:
The low-cost VNA used for these measurements has the capability to display the parameters S11 and S11 in an admittance Smith Chart (Figs. 7 and 8). The advantage of displaying an S-parameter in an admittance Smith Chart is that according to Eqs. 4 and 6 and ref. 7, this representation yields directly the values of Yic and Yis. Furthermore, when using the VNA's marker functions, admittances Yic and Yis are characterized by their real parts (conductance G), and imaginary parts (susceptance B). (refer to Figs. 7 and 8). Therefore, in order to exploit optimally the VNA data, it is worth expressing the differential input admittance Yid (Eq. 9) directly with the conductances and the susceptances of Yic and Yis, respectively:
Substituting Yic and Yis into Eq. 9, by the expressions given respectively by Eqs. 10 and 11 yields the real and imaginary parts of the differential input admittance:
Nevertheless, when performing impedance matching, designers typically use the input and output impedances of the load and the generator to be matched, respectively. Therefore, it is worth calculating the differential input impedance:
After inversion of expression 12, one can find the real and imaginary parts of the differential input impedance:
It is important to note that the accuracy of the differential input admittance or impedance calculated with respectively expressions 12 through 15 is strongly dependent on two sources of errors:
1. The imperfection of the AC short circuits produced by the coupling and bypassing capacitors, CC1, CC2, and CBP, respectively, in Figs. 3 and 4.
2. The quality of the calibration performed when using the VNA.
Concerning the first source of error, making an AC short circuit at high frequencies is not a trivial task, especially when the bandwidth is large. Fortunately in the particular case of narrowband matching, this potential issue can be avoided thanks to a technique called "tuned decoupling."8,9 This technique consists of looking for the decoupling capacitor or decoupling circuit that exhibit the lowest impedance possible for the frequency of interest, for example, a capacitor with a first self-resonant frequency (SRF1) which coincides with the frequency of interest. Another example is a capacitor and the associated wiring self-inductances that form a series resonant tank circuit tuned to the frequency of interest.
The first case is certainly the best solution, but the exact coincidence of the capacitor's SRF1, with the working frequency is rarely encountered. The second case constitutes the general case of tuned decoupling (which encompasses also the first case). Tuned decoupling is a two-step process:
1. The VNA is used to select a capacitor having an SRF1 above the frequency of interest.
2. The selected capacitor is connected by two traces between the two points to be AC short circuited (points A and B in Fig. 5). The total length, l = l1 + l2, of the traces is then determined for producing a series resonance between points A and B at the frequency of interest (fW). The total length (l) of the traces can be approximately calculated with the equivalent circuit in Fig. 5. The frequencies of resonance of the capacitor alone (SRF1), and of the tank circuit between points A and B (frAB) are, respectively:
where:
LC = the equivalent series self-inductance of the capacitor,
L = L1 + L2 represents the self-inductance of the total length of the traces (l = l1 + l2), and
fW = the working frequency.
After substitution of LC in Eq. 17 by its expression given by Eq. 16, one can finally draw from Eq. 17 the self-inductance of the total length of the traces:
Assuming that the self-inductance per unit of length of a printed-circuit-board (PCB) trace is about 1 nH/mm, the total length of the connecting traces is approximately given by:
where:
l(mm), is the total length of the connecting traces expressed in millimeters.
This two-step tuned decoupling technique has been applied at 40.68 MHz for the coupling capacitors CC1, CC2 in Figs. 3 and 4, and the bypass capacitor CBP in Fig. 4. Knowing that the length of the viahole to the ground plane must be added to the connection length of a bypass capacitor (+1.6 mm for a standard FR4 epoxy glass board), two capacitors were selected with values of 5.6 nF and 3.3 nF. The table shows the electrical characteristics of these capacitors, and the associated values of the total length of the connecting traces calculated with Eq. 19.
From the table, one can see that with a required connection length of about 2 mm, a 5.6-nF chip capacitor is an optimum choice for the coupling capacitors CC1 and CC2, while a 3.3-nF chip capacitor that calls for a connection length of about 4 mm is well suited for performing a bypass to ground (capacitor CBP). It is important to note that the total length of the connecting traces calculated with Eq. 19 are approximate values, consequently the bonding pads of the capacitors have been enlarged of ±2 mm for performing an experimental tuning.
The second source of error mentioned above is calibration of the VNA. According to Agilent Technologies (Santa Rosa, CA),10 the best calibration technique at RF is the standard short-open-load-through (SOLT) calibration. If the test fixture is equipped with 3.5-mm SMA connectors, a model 85033D 3.5-mm calibration kit from Agilent Technologies is typically used. But this calibration kit moves the reference plane to the connector's outer conductor mating surface (plane P1 in Figs. 3 and 4), and not to the measurement plane (plane P2 in Figs. 3 and 4). Consequently, a second operation is needed to shift the calibration plane to the measurement plane. This operation can be performed with the VNA's port-extension function (mathematically modelling the test fixture) or with de-embedding software.10 Nevertheless, each method has limitations that produce additional errors. In order to avoid these errors, an efficient solution at RF is to move the calibration plane directly to the measurement plane using a technique called the direct measurement method.10
Direct measurement involves measuring physical calibration standards exactly in the same plane as the device under test (DUT) measurement plane and calculating error terms. With this method, the precise characteristics of the fixture do not need to be known. They are measured during the calibration process. From the start, the direct measurement method is a four-step process:
1. A user calibration (cal) kit must be built. Figure 6 shows the SOLT user cal kit used for the Philips' receiver. The short, open, and 50-Ω load are located at the end of a microstrip line having a length of 14 mm and 50-Ω characteristic impedance. Consequently, the through standard is a 2 × 14-mm long microstrip line having the same characteristic impedance.
2. The standards must be characterized: Fortunately, at RF, only the open standard requires characterization (because an unterminated microstrip line radiates energy). This characterization consists in determining the fringing capacitance of the open in the frequency band of interest. The method for measuring an open standard is detailed in ref. 10.
3. The standard definition table of the cal kit must be entered into the VNA's memory. With an Agilent VNA, this step is quickly performed by modifying an existing calibration kit.11
To minimize the number of standards to modify, it is wise to select a cal kit whose characteristics are as close as possible to those of the user kit. In the case of the kit shown in Fig. 6, the best solution is to modify a calibration kit in which the physical calibration standards are measured in the plane of calibration. The APC7 calibration kit matches this definition. With such a kit, the modification procedure is reduced to entering the fringing capacitance of the open standard:
When using an Agilent VNA, the fringing capacitance (CF) is modeled as a function of frequency by a cubic polynomial that best fits the fringing capacitance measured in step 2:
The coefficients: C0, C1, C2, C3 must be entered in the VNA to fully characterize the open standard. For the cal kit shown in Fig. 6, these coefficients were found to be C0 = 3.7 × 10-15 F, C1 = 2100 × 10-27 F/Hz, C2 = 0, and C3 = 0.
4. The DUT must be mounted on the test fixture in such a way that the calibration reference plane (P2) is linked to the board edge SMA connector by a 50-Ω microstrip line having the same length as the ones of the user calibration kit (14 mm for the cal kit shown in Fig. 6).
At first glance, this four-step process appears time consuming. But once the user kit has been built, characterized, and entered into a VNA, only a single task must to be performed for testing a new device (the last step).
This differential test procedure has been applied to the mixer characterization at 40.68 MHz for the Philips UAA2080T receiver IC. Parameters S´11 and S´´11 were measured with the VNA and the results can be seen in Figs. 7 and 8. Figure 7 shows S´11 for the mixer's balanced RF input ports (pins 12 and 13), mounted in the common-mode input admittance test circuit of Fig. 3. Marker 1 yields directly the value of the common mode input admittance Yic:
Figure 8 shows S´´11 for the mixer's balanced RF inputs (pins 12, 13) mounted in the difference-mode input admittance test circuit of Fig. 4. Marker 1 yields directly the value of the difference mode input admittance Yis:
Substituting the values of the conductances and susceptances given by Eqs. 21 and 22 into Eqs. 14 and 15 yields finally the DUT's differential input impedance:
Knowing the value of the differential input impedance, it was then possible to both perform an accurate impedance matching between the balanced LNA's outputs and the differential inputs of the mixer and to control the 90-deg. relative phase difference between the I and Q channels.
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