Communications-system design is complex, requiring practical and powerful design tools. Complex interactions between RF components, baseband signal processors, and increasingly complex modulation schemes can challenge even the most experienced designer. Fortunately, modern electronic-design-automation (EDA) technology can help overcome these challenges with a more seamless design flow. What follows is an examination of a top-down/bottom-up design-flow approach based on the use of advanced EDA tools. To demonstrate the approach, an IEEE 802.11a wireless local-area-network (WLAN) integrated-circuit (IC) design will be used as an example, although the principles are applicable to other communications standards and other design topologies, such as RF printed-circuit boards (PCBs) and multichip modules (MCMs).
To create a communications architecture, an engineer must consider the technical boundary conditions of the physical layer (PHY). Consider a WLAN based on offset frequency-division-multiplex (OFDM) signals. Data rates to 54 Mb/s are achieved by using higher-order quadrature-amplitude-modulation (QAM) formats and 53 subcarriers that share frequency spectrum with adjacent orthogonal subcarriers. With these lower-rate parallel subcarriers, the relative amount of time dispersion caused by delay spread is decreased, and with an adequate guard interval, intersymbol interference (ISI) is almost eliminated. While these characteristics make for a high-speed communications link, they also introduce design challenges:
- Sensitivity to frequency offset—good frequency correction is needed in the receiver (Rx) to ensure good inter-carrier interference performance (ICI).
- Sensitivity to oscillator phase noise for best bit-error rate (BER) at high order QAM.
- Channel estimation is used to detect and remove delay spread.
- The complexity of inverse Fast Fourier transform/Fast Fourier transform (IFFT/FFT) required to optimize latency and performance.
- Maintaining orthogonality under high-power conditions.
- High peak to average ratios strain power-amplifier (PA) performance.
Due to the complex modulation scheme of OFDM signals, with multiple subcarriers and critical timing requirements, performance of the system cannot be determined unless the modulation is considered, circuit interactions are taken into account, and RF/baseband interactions are evaluated. Considering the issues, it is no wonder that communications-system design is complex and time consuming. But if an EDA tool has a design and verification environment that is tailored to the communications standard, a designer should be able to generate a viable design is less time, and quickly verify it to obtain the best chance at a first-pass success.
The basic system design flow is a top-down, bottom-up design flow following these steps:
Optimize system design
Functional block/circuit design
Functional block verification
This top-to-bottom flow involves RF and analog-mixed-signal (AMS) design that can be used for RF system/baseband and digital-signal-processing (DSP)/baseband system designs, which are typically designed in parallel. For RF/mixed-signal IC applications, this design flow is currently undergoing further refinement by Agilent Technologies (Santa Rosa, CA) and Cadence Design Systems (San Jose, CA) as part of a five-year technology alliance announced in February.
To handle the WLAN example, Agilent Ptolemy, a dataflow manager with embedded system design capability that is available in the Advanced Design System (ADS) design environment from Agilent Technologies, will be used. The ADS design and verification environment library available for WLAN 802.11a will also be used.
Before proceeding, it might help to review some of the EDA tool attributes (see table) that should be examined prior to taking on a complex design such as a WLAN. RF/baseband and DSP/baseband engineers typically collaborate to determine architecture partitioning. Algorithm-based tools and spreadsheets play an important role in this design area and it is often desirable to import or re-use these algorithms in the system-design tool. Since each communications standard (such as IEEE 802.11) puts different constraints on the system design, intellectual-property (IP) reuse from one system to another will be minimal in many cases, although it would be desirable to have access to IP specific to an application to speed the design process. Fortunately, within ADS, the Agilent WLAN Design Library and WLAN DesignGuide provide much of the needed application-specific expertise to simplify a WLAN design.
A rough idea of the RF/mixed-signal design partitioning can usually be developed early in the conceptual design phase. To speed this process, a reference Rx, for example, is available in the WLAN DesignGuide that can be used as a baseline in establishing an architecture for the WLAN Rx. In this case, a zero-intermediate-frequency (IF) Rx is suggested. The architecture allows a significant simplification and reduction in analog parts count, and increases flexibility of the Rx. In terms of specific design advantages, this architecture also simplifies the frequency-offset problem encountered in WLAN designs by reducing the number of elements that contribute to frequency errors.
Figure 1 shows a high-level Rx block containing the baseline architecture IP in the WLAN DesignGuide. Pushing down into the next level of system hierarchy reveals more of the architectural details. The simulation results show the system automatic-gain-control (AGC) response using the AGC test available in the DesignGuide. To speed the design process, it is desirable to reuse as much existing IP as possible. This may include behavioral models of RF front ends, circuit high-definition-language (HDL) functions, functional cores, and algorithm import. All of these functions can be used to provide essential implementation paths for circuit and baseband-circuits implementation. By using a simulation backplane similar to Agilent Ptolemy, proven IP such as that used in channel estimation can be reused or refined.
Once the base Rx architecture is determined, the design can be refined using the WLAN library functional blocks, and the ADS hierarchical optimizer available at the system level. At this point, propagation models can also be added to form the basis of a more realistic simulation, and further refinements made if necessary. Verification is the process of performing a detailed check on a design during its development, to determine its viability before proceeding to the next step. Once a first-pass design of the system architecture has been completed, it needs to be verified against the wireless standard before it is implemented.
System-level verification can be performed using the various test benches available in the ADS WLAN Design Library. In the library, a full range of tests is available to verify the PHY design to a specific communications standard revision. A user can elect to insert a subsystem, block design, or circuit and test performance against the WLAN standard. After block implementation, the verification process must be performed again prior to fabrication. After determining a functional system design, system designers usually provide specifications for the functional RF and baseband blocks used by circuit/baseband designers who design the blocks in a form that can be implemented. Synthesis of the active RF and baseband blocks directly may be desirable, but with the high performance requirements, advancing technology, and need for efficient design implementations, designers often do not to embrace these types of tools.
Functional block design usually occurs with a separation between the RF and baseband worlds. One activity of the alliance between Agilent and Cadence is the development of tools which more seamlessly transfer IP back and forth, to support a more comprehensive design flow that permits greater interaction between RF and baseband designers.
As part of RF/baseband-system-block design, these function blocks must be intimately linked with the system-design environment so the effect of RF/mixed-signal interactions and physical design can be analyzed. Due to the complexity of modern modulation schemes, simple frequency-based simulation is no longer adequate for simulations of wireless-communications function blocks. Even a frequency-based simulator may need to simulate multiple tones with many harmonics and robust harmonic-balance simulators with Krylov subspace solvers and pre-conditioners are needed to obtain the accuracy required in a reasonable amount of time.
Ultimately, however, harmonic-balance simulation is not adequate by itself to analyze complex digital modulation represented by time-varying phase and amplitude information in circuits. WLAN modulation has a very-high peak-to-average ratio that challenges the capabilities of many amplifiers and disturbs the complex vector information, which degrades orthogonality between channels. This degradation cannot be identified with harmonic balance simulation, which is a frequency-based technology with no time-varying information. A better approach is the use of an envelope simulator that uses complex digital modulation for analyzing the effects of modulation on a design. Agilent's patented Circuit Envelope technology allows the engineer to simulate circuits embedded within a system design in this matter.
Time-based simulation is often overlooked, but dynamic-circuit problems are a major reason why some designs do not achieve first-pass success. For example, the WLAN signal contains a vector, and in an AGC-controlled amplifier chain, dynamic effects of the AGC and PA can distort this vector and cause data errors. Time-based simulation such as Simulation Program for Integrated Circuit Emphasis (SPICE), Convolution, and Circuit Envelope can analyze the dynamic effects of PA droop, phase-locked loops (PLLs), modulators/demodulators (MUX/DeMUX), and RF switching time. Circuit Envelope is also the only commercial simulator that can analyze many of these problems and directly provide the engineer with dynamic frequency versus time information for behavior such as oscillator start up.
WLAN 802.11a circuits involve frequencies in the 5-GHz range, and the physical aspects of the RF design in a dense packaging environment can mean trouble for the circuit designer. An electromagnetic (EM) analysis tool with sufficient speed and capacity can provide valuable insight into potential problems. Tools such as Momentum from Agilent incorporate mesh reduction and quasistatic solvers that enable EM simulation of whole new classes of problems such as signal crosstalk and SMT/BGA packaging analysis. Having a fully integrated EM tool combined with other simulation engines provides many benefits. For RF circuit design, engineers can use a combination of time-domain simulation technology from Cadence and frequency-domain simulation technology from Agilent, including the new RF Design Environment (RFDE) product, the first product available as a result of the Agilent/Cadence alliance. Once the circuit design has been completed, the ADS Ptolemy environment can dynamically link to RF circuit schematics in the Cadence environment for circuit/system verification.
Baseband/DSP designers have their own sets of problems to overcome. Typically, they operate in a nonschematic environment and use the fixed-point specifications handed to them. Their work involves fully synthesizing gates, hand-coding RTL, or reusing IP that is represented using a hardware description language. As noted earlier, channel-estimator design can be tricky for WLAN systems. There is a need to consider the RF impairments, since they affect the way the DSP timing and clock analysis is done. Therefore, if the RF/baseband and DSP/baseband design can be done in the same environment, IP can be shared between both sets of system designers facilitating the design process.
Once the RF and baseband circuits have been designed, it is desirable to place the block-implementation circuits or RTL back into the system design to check interoperability and verify overall system performance. This is performed using block-substitution methods. System designers can import baseband design blocks into the system-simulation environment using high-definition-language (HDL) wrappers. On the circuit-block side, behavioral model extractions, or more detailed circuit cosimulation is used to port the circuit-block data back to the system designer. Behavioral model extractions can speed up the simulation process at the expense of circuit-behavior detail. These types of simulations allow the designer to validate their system design to a certain level of detail. A comprehensive circuit/system co-simulation is best done using a tool like Circuit Envelope. Using these two processes, a system-verification process can take place.
System verification is best performed using the WLAN library. The Agilent product includes various test benches and is, therefore, more than a library of functional block models. Its value to the WLAN designer includes the ability to simulate the design and verify it to 802.11a standards. This includes testing of adjacent-channel power ratio (ACPR), error-vector magnitude (EVM), BER, and packet-error rate (PER). Verification is done by simply placing the appropriate design block, subsystem or system in the applicable test bed provided in the WLAN library product and running a simulation in ADS. The results are displayed graphically, and include the pass/fail criteria for the 802.11a standard. Various revisions of the standard are provided so testing can be performed to the specified revision level.
Figure 2 shows a WLAN PA block being verified with a subsystem design in the WLAN design and verification environment. In this example, the amplifier could be a behavioral functional block, a circuit design, or a representation of measured data. Preconfigured tests in ADS can verify circuits and systems, including tests such as EVM, BER, and PER. A fully coded BER verification will provide a meaningful verification that includes not only the RF interactions, but much of the baseband processing as well. This enables the engineer to evaluate IFFT/FFT complexities in equalizers, channel estimators and coders/decoders (codecs), providing the engineer with confidence that the system will have the best chance at a first-pass success and not require expensive design revisions.
Figure 3 offers an example of WLAN transmitter (Tx) verification. This plot shows spectral regrowth of a PA evaluated at an output level of 200 mW. The complete Tx chain can also be evaluated in this manner. These test benches are available for a number of WLAN-related specifications for T/R paths. The capability of connecting simulation and measurement tools is a tremendous advantage when modeling and verifying the performance of modern communications systems. With compatibility between simulation tools and test instruments, for example, complex modulation formats defined in software can be saved as digital files for digital-signal generators to produce a wide range of arbitrary waveforms. The compatibility of EDA and test instrumentation (available from Agilent Technologies) allows designers to leverage encryption algorithms, to leverage connectivity algorithms between the EDA environment and the test bench, to share signal-generation code, and to support two-way communications between simulators and analysis tools, such as BER testers and vector-network analyzers (VNAs).
This "connected-solution" approach allows virtual prototyping where a new WLAN design can be tested with existing components, by exporting simulated signals to test hardware inputs and then pulling the test hardware outputs back into the simulator for processing. The approach also makes it possible to emulate the behavior of a WLAN hardware block by importing signals from a hardware output, processing the signals in the simulator environment, and exporting the resulting processed signal back to a hardware input. It also simplifies debugging and troubleshooting of designs and makes it possible to create custom test beds for evaluating the performance of new designs.
Upon successful functional block/system verification, a system design is nearly complete. Lower-level layout floorplanning, synthesis, timing and baseband implementation have been brought to the physical-design step. After fabrication, the system designer can use the embedded IP and test vectors generated within Agilent Ptolemy, plugging them into a connected solution for hardware verification and prototype testing. For more information visit www.agilent.com/find/eesof.