Pulsed current-voltage (I-V) testing is becoming an invaluable method for evaluating the performance and reliability of semiconductor devices. The measurement approach is relatively cost effective and avoids the negative effects of self-heating and transient trapped charges, which can result in misleading test results. And pulsed I-V testing provides the accurate device data needed for improved computeraided- engineering (CAE) software models.
Pulsed I-V testing is based on the use of a pulsed source to stimulate a transistor or device under test (DUT), followed by a pulse measurement on the device. Since RF transistors are primarily used in applications where nonlinear responses are common, such as switches and amplifiers, large-signal analysis is typically the goal of pulsed I-V testing. The two main test methodologies are pulsed I-V sweeps and transient (singlepulse) testing (Fig. 1). By using a dual-channel pulse source/measurement system, this type of testing can be simply and cost-effectively performed.
Pulsed I-V measurement sweeps produce results similar to familiar DC tests, such as curves showing drain voltage VD and drain current)ID behavior under different bias conditions. This means the base of the pulses have a non-zero value for both gate and drain voltage, often referred to as the operating point or quiescent (q) point. The technique in this type of testing is application of a low-duty-cycle pulse (typically less than 1 percent duty cycle) to the DUT, to avoid self-heating and carrier-trapping effects. As shown in the left-hand side of Fig. 1, each point on the curve is the result of a pulse measurement made on the DUT during the settled or flat portion of the pulse. In practice, many pulse measurements are averaged to improve the quality of the overall measurement results.
The second type of pulsed I-V testing is the transient or single-pulse test (right-hand side of Fig. 1). In this case, the test results are presented as a view of the measurement pulse or an average of multiple pulses. The measured signal is plotted as the DUT's voltage or current versus time, showing any time-varying changes, such as the onset of self-heating or charge trapping.
A wide range of pulse widths can be useful for performing pulsed I-V testing, depending on the DUT or material type and test parameters. For millisecond pulse widths, standard source-measure units (SMUs) can be used. However, shorter pulses (microseconds to nanoseconds) are generally more effective for avoiding selfheating and charge-trapping effects. Therefore, short-pulse pulsed I-V testing of RF transistors generally allows the creation of more useful models.
A useful dichotomy in describing RF transistor characterization is the distinction between small-signal and large-signal testing. Small-signal (Sparameter) data is useful for accurately representing linear devices, such as cables, filters, connectors, and couplers, i.e., devices governed by Maxwell's equations, which produce linear responses with time and frequency. This means that S-parameter extractions require linear responses to feed the modeling process. In contrast, RF transistors are primarily used in applications where nonlinear responses are commonplace, so large-signal analysis is most useful for evaluating such devices under real-world conditions.
Various approaches are available for performing large-signal analysis, including the use of a large-signal vector network analyzer, non-50-ohm measurements, and pulsed I-V testing. Large-signal network analysis extends a measurement approach and instrumentation that is well characterized for small-signal measurements into the large-signal domain, where less history and documentation is available. A consensus on the theoretical basis of this methodology is still being developed, and the present installed base is relatively small. In addition, there are challenges in using the hardware to create and control the large signals that are required.
Two common approaches are used for testing RF transistors in non-50- ohm environments. The load pull approach uses a manual or programmable impedance tuner to vary the impedance at the output of the transistor (or other active device), then measures various performance parameters such as gain, compression, saturated power, efficiency, and linearity under those changing-impedance conditions. The output load is varied across several areas of the Smith Chart to achieve a full understanding of the device's behavior. The sourcepull method varies the impedance seen at the input of the transistor while measuring the desired parameters, including the signal-to-noise ratio (SNR).
Pulsed I-V testing also permits the use of large signals and is fairly straightforward from a theoretical basis. The key advantage of pulse testing is the ability to leverage an extensive body of knowledge from DC modeling and analysis. In addition, it avoids self-heating and charge-trapping effects in the DUT. The three different large-signal analysis methodologies are not, in general, competitive and often, multiple approaches are used to characterize a DUT's large-signal behavior.
Pulsed I-V testing carries with it certain requirements in terms of test techniques and instrument capabilities. These include:
- pulsing from a nonzero base or value (i.e., bias point/ quiescent point/DC offset);
- bias voltage pulsing of both the gate and drain;
- employing scaled-down test structures or devices, and lower power than the typical operating point for highpower RF transistors;
- using a current-sense resistor along with a software routine for load-line compensation;
- applying a software routine for cable and other interconnect compensation; and
- employing the appropriate tools to address system and device oscillation.
Fortunately, commercial instruments are available to provide all of the features needed for effective pulsed I-V device testing.
Figure 2 shows a nonzero bias point (the red lines on the right-hand side), also referred to as the quiescent point or q-point, based on pulsed I-V sweeps. The nonzero value, for both the device gate and drain, results in a point in the VD - ID plot marked by the red "X" in the left-hand side of Fig. 2. The pulse waveform as a nonzero base, represented by the red features in both sides of Fig. 2.
During an I-V sweep, the pulse height is varied as shown in the right diagram of Fig. 2. Measurements are made within the pulse as detailed by the black arrows on the right. The measurements are also shown in the left-hand side of Fig. 2, as black arrows pointing toward the measurements and away from the q-point. This indicates that the device is returned to the q-point condition between every measurement.
Figure 3 illustrates a pulsed I-V sweep in the testing of a depletionmode transistor. A depletion-mode transistor is normally on with 0 V bias at the gate, with a negative voltage applied to the gate to turn off the device. Pulsed I-V testing of a depletion- mode transistor requires a VG bias point that is negative to either partially or fully turn on the DUT. In Fig. 3, the device is turned on partially by using a small voltage for VG and VD. The VG sweep starts at a negative voltage and sweeps to slightly above 0 V. Voltage VD is swept from 0 to 27 V. This example also shows a negative bias point (q-point) for the gate, and a positive q-point for the drain. The pulse waveform, including the bias point (DC offset), is provided by the pulse instrumentation.
Pulsed I-V testing requires an instrument with dual-channel capabilities for comprehensive q-point testing, as shown for testing depletion-mode transistors. While it is possible to perform pulsed I-V testing with a DC bias on the transistor drain and pulse only the gate, this may not cover all DUT test conditions of interest. While a DC bias on the drain provides a simple test method, it does not allow a q-point value to be used for both the gate and drain when doing a VD-ID test, because the drain signal is always sweeping and is not at the VD bias point. To support full bias point operation, both the gate and drain must be pulsed simultaneously.
Many RF transistors are used for power amplification and may handle power levels to 200 W. A pulse source capable of this power level would be expensive. Therefore, to control costs and simplify testing requirements, the DUT is usually a scaled-down version of the transistor to be characterized (Fig. 4), although even a smaller device can require around 30 W of pulse power for pulsed I-V testing.
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Figure 5 shows a simplified block diagram for pulsed I-V q-point testing. It contains SMUs that independently bias gate and drain during DC testing. Similarly, independent pulsers supply the VG and VD pulse stimuli to the DUT. The SMUs and pulsers are connected and disconnected from the signal paths via on-board switching. The switching in this block diagram is shown in a standby condition (switches open), with the test equipment disconnected from the DUT. During pulsed I-V testing, the SMUs are not connected to the device under test. Naturally, the pulser used for the drain has higher power capabilities than the one used for the gate. Although shown as separate blocks in the diagram, the two oscilloscope channels are provided by a single unit in the actual test system, allowing independent measurements of the DUT gate signals and drain responses.
In this system, the gate pulse source has 50-ohm output impedance, while the drain pulser has 55-ohm impedance. The latter condition is due to an added 5-ohm sense resistor (circled in blue) to derive the drain current and voltage. The technique of measuring voltage across a sense resistor to capture current uses a simple shunt ammeter circuit, which provides high bandwidth and is straightforward in its implementation. The voltage across the 5-ohm resistor, Vsense, is measured on channel 2 of the oscilloscope module.
The shunt ammeter approach does have trade offs, chiefly the reduction in applied drain voltage. This is commonly referred to as the load line effect and is a direct result of using a sense resistor to measure drain current. As drain current flows, there is a voltage drop across resistor Rsense. The voltage drop means that voltage V} is not the same as the voltage at the drain pin, VD'. If this drop is not taken into account, then the family of curves is limited to the load line of Rsense, as shown by the graph in the right view of Fig. 6.
Fortunately, load-line-compensation (LLC) algorithms can correct for this effect. In addition to providing the desired test voltage range, the LLC algorithm provides the regular spacing, or stepping, of the voltage during the VD sweep. Thus, a full VD - ID characterization of the DUT is achieved. This also means that post-processing of the measured data to determine VD values "on grid" is eliminated, reducing the time required to get test results from the measurement system to the modeling software.
Cables and interconnections should be carefully considered in any pulsed I-V measurement system, since cables can introduce propagation delays and degrade measurement accuracy. Cable and interconnection impedances must be determined and corrected in order to achieve high measurement accuracy with a pulsed I-V test system. This requires a cable compensation routine that measures and corrects for these attributes. For example, in the Keithley 4200-SCS PIV system, it is a simple, short procedure used during initial setup and after any cabling or other interconnect changes. Since the routine includes a through or short test, even pin-to-pad impedance is incorporated into the compensation.
Another problem in testing RF transistors is the potential for oscillations. These disturbances are due to high device cut-off frequencies (much greater than 1 GHz), coupled with the inherent instabilities created by intrinsic (device) and extrinsic (instrument) feedback paths. These conditions are exacerbated by the fact that the test environment cannot completely match the product environment. Typically, testing requires a wider range of parameters than found in a product's application.
For an experienced pulsed I-V user, it is usually straightforward to identify oscillation, or even detect the onset of oscillation, by viewing the characteristic shape of the pulsed I-V plots. For new structures and devices, or less experienced users, however, a more direct method of oscillation detection may be useful. In these cases, looking at an oscilloscope display of the actual pulse is quite helpful. This permits visual confirmation of oscillation and can demonstrate whether a particular remedy has suppressed it.
In general, oscillations can be controlled by reducing loop gain, which is done by adding capacitance or inductance. But the added reactance can have an impact on system bandwidth and can reduce the pulsed I-V test performance. It is usually simpler to add resistance, which has less effect on system bandwidth.
When adding resistance in a DUT's feedback path, also known as ballast resistance, the added resistance must not impede the pulsed I-V measurements. The test instrumentation must also be able to account for the added ballast resistance and provide corrected results.
When pulse testing RF transistors, a series resistance is appropriate for the gate, and a parallel resistor can be placed between the source and drain (Fig. 7). In the latter case, the shuntto- ground resistance is designed to reduce loop gain while counteracting the effect of negative slopes on the I-V curves (i.e., negative differential conductivity). Ballast resistance may be added in either or both locations. Ballast resistors are used to reduce or eliminate oscillation, but with the cost of reduced voltage and current at the DUT. For example, in Fig. 7, all the current flowing through shunt resistor RSH on the drain is not available for the DUT drain. Determining the use of ballast resistors and their resistance values involves a qualitative, iterative process. However, some commercial test systems may come with a set of low reactance resistors, plus software routines that correct test results when ballast resistors are used.
Figure 8 shows a screen capture of test results comparing pulsed I-V and DC sweeps. It clearly shows the effects of self-heating caused by DC testing in the middle and upper sets of curves. Note that in the lowest power curves (bottom set), the DC and pulsed I-V test results are virtually identical. However, ID in the top (pulsed I-V) curve of the upper set is about 230 mA (50 percent) higher than the blue DC curve. In the latter, significant self-heating has caused a collapse in the ID characteristic.
Single pulse tests can be used to characterize transient behavior and to check for oscillations. Figure 9 illustrates typical results. The blue curve is the voltage pulse applied to the gate, and the red curve is the resulting drain current. Both curves are well behaved, without any overshoot, ringing, or oscillation. When verifying a setup, viewing the pulse shape can be valuable to ensure that proper cabling and contact to the device pads has been made.
When examining a DUT's transient behavior, a time-varying change in the device response can signal self-heating, charge trapping, or other time-varying phenomena. Figure 10 is an example of self-heating that causes a reduction in drain current as a function of time. In Fig. 10, ID starts at about 630 mA, but down to 590 mA after 10 ms, which is a reduction of about 6 percent.
Dual-channel pulsed I-V testing with nonzero bias on the gate and drain of RF transistors is a powerful test tool. It allows accurate characterization under a wide variety of conditions that simulate large signal (nonlinear) operation. With appropriate test hardware and software, a wide variety of single pulse and multiple sweep test routines are available and easy to run. (See, for example, the test list on the left side of Fig. 8.)
Many times, device characterization is an iterative process, therefore a measurement system designed for interactive testing is highly desirable. Important features of such a system should include a wide range of pulsed I-V parameters for different transistor types, such as high electron mobility transistors (HEMTs), pseudomorphic HEMTs (pHEMTs), and laterally diffused metal-oxide-semiconductor (LDMOS) transistors. The test system should also provide submicrosecond pulse-timing parameters, including delays, and capabilities to modify test parameters and compare new results to previous results on the fly. The system should also support comparison of DC and pulsed I-V test results for dispersion effects, provide comprehensive data analysis and simple means for exporting data into other applications. Overall, the system should include interconnections and measurement software that enable q-point testing and cable compensation, LLC software routines, and ballast resistors to control oscillation, with flexible measurement software that can correct for the test results when ballast resistors are used.