This rugged bipolar transistor has been designed to withstand high levels of ESD making it well suited for UHF automotive electronics applications.
Automotive applications in the ultra-high-frequency (UHF) band require transistors that provide good RF performance but are also robust. The BFP460 from Infineon Technologies (Munich, Germany) is a general-purpose transistor that is electrostatic-discharge (ESD)-hardened for such applications. It benefits from a silicon-bipolar process technology with 23-GHz transition frequency and can safely withstand ESD pulses of 1500 V between any pair of terminals. The effectiveness of the new device will be demonstrated in a UHF low-noise amplifier (LNA) that is ideal for automotive use.
A variety of automotive systems now make use of RF technology, including remote-keyless entry (RKE), Global Positioning System (GPS), Satellite Digital Audio Radio Services (SDARS), and tire-pressure monitoring systems (TPMS). Each of these systems require RF building blocks having good performance, low cost, and high levels of ruggedness/robustness (Table 1).
As RF devices have scaled to smaller dimensions for higher-frequency use, they tend to exhibit higher current densities (approximately 3 mA/µm2 or 300,000 A/cm2 at a typical transistor operating point) while the breakdown voltage has dropped (from typically 50 V to around 3 V). The breakdown voltage as well as the optimum current density is determined by the thickness and the doping of the collector. For a high transition frequency, the collector must be kept thin. For high gain, all internal parasitic capacitances must be kept small, which is a driving factor for shrinking lateral dimensions, but also makes a transistor more sensitive to ESD damage.
Rigorous study of transistor ESD failure mechanisms have shown that there is room for improvement in device ESD robustness. The discrete BFP460 transistor incorporates some of the findings of such research to withstand 1500-V human-body-model (HBM) pulses while achieving a cutoff frequency of 23 GHz, maximum stable gain of 17.5 dB and minimum noise figure of 1.1 dB at 1.8 GHz.
The most widely used standard for ESD testing is the HBM detailed in MIL STD 883D. In this standard, a 100-pF capacitor is charged to a reference voltage (VREF). The reference voltage power supply is then disconnected, and the capacitor is discharged while connected through a series 1500W resistor to the device under test (DUT). This circuit setup may be viewed as a current source. Reference voltages as low as 100 V are used for low-noise transistors with small device geometries and higher sensitivity to ESD, while voltages to 5000 V are used for older, lower-performance, larger-geometry transistors (Tables 1 and 2 in ref. 4). A DUT is considered "rated" for a particular ESD level when it shows no degradation or failure when subjected to such tests at that level of VREF. Typically, such tests have been performed on packaged devices, although ESD testing is now also possible at the on-wafer chip level. As an alternative method to the Human Body Model, the transmission-line pulse measurement (TLP) is often used to assess ESD tolerance.
An ESD pulse can best be understood as a rapid surge of current within the device. For a first-order approximation, it is valid to assume that this event occurs too quickly to permit heat to spread or dissipate within the device experiencing this current surge. As a result, the temperature increase resulting from the ESD induced current surge is proportional to the square of the current density, and there exists a limit current density level beyond which actual localized melting of the device's silicon occurs. It is in fact this melting of the silicon material which leads to device failure. As current density is the key item leading to device failure, transistors with a large emitter periphery or large area are more rugged than smaller ones. Contrary to common belief, there is little correlation between a transistor's collector-emitter breakdown voltage (VCEO) and its resistance to ESD damage.
For improved robustness, designers of RF integrated circuits (RF ICs) have developed internal ESD protection structures which help shield the ESD-sensitive RF input and output terminals from harmful ESD events.1,2 Unfortunately, these ESD-protection structures also "load" the RF terminals with stray capacitance, inductance, and losses, thereby causing degradation in performance and making such structures unsuitable for use with discrete devices (where higher performance is expected).
In a three-terminal device like a bipolar transistor, there are six possible ways to apply an ESD pulse across any two of the device's terminals, while the unused device terminal remains "open" (not connected). Usually, the transistor is most susceptible to damage when ESD pulses are applied across the positive-negative (PN) junctions in a reverse direction. While dependent on specific semiconductor process technology, the collector-base junction is usually the weak link in an RF transistor.
During an ESD event, the base-collector space-charge is driven down into the highly doped substrate or (buried layer in RF ICs).1 This situation is very similar to the so-called Kirk-effect. Nearly all of the transistor's voltage drops over the collector-substrate boundary, yielding increased field strength in this region (the density of free electrons in the collector region has surpassed the doping density). Since the free electron charge in the collector must be compensated by a counter charge, the only region where it can be built up is in the highly doped substrate (or buried layer).2 If this field reaches the internal breakdown field strength of approximately 3 x 105 V/cm in the case of silicon, massive impact ionization occurs. More free carriers are generated (electrons and holes) and a runaway process takes place, with external voltage breakdown. This effect is called "second snapback" in ref. 1, after the VCEO snapback effect.
Most of the energy contained in the ESD pulse is released at the site of the highest field strength which increases the local device temperature. This in turn increases the number of free carriers due to the intrinsic conductivity mechanism. The process continues its downward spiral via a positive feedback mechanism and as a consequence the current tends to focus onto an ever smaller spot with subsequent melting and burnout of silicon material.
To some extent, the addition of a distributed series resistance to the current path can help avoid the concentration of ESD-induced surge current.3
The series resistance forces an even distribution of surge current, and helps avoid the subsequent destructive mechanism. Careful design of a transistor cell can also help avoid such destructive effects. For example, any crystal defect, any sharp edge, any abrupt corner may cause a resulting increase in localized electric field strength; such defects should be avoided.
A straightforward way to reduce ESD-induced fields is by choosing a lower doping density in the substrate in order to distribute counter charges more deeply into the substrate. Unfortunately, this approach affects the substrate resistance (and RF performance). A better way is to insert a buffer layer between the substrate and the active collector region.5 The dopant concentration of this buffer region must be higher than the active collector region, but lower than that of the substrate; still, it must be high enough for the buffer to serve as a substrate under normal operation (Fig. 1). This design approach was employed in the BFP460 to boost ESD tolerance from 300 to 1500 V (for a packaged device with 64-µm2 emitter area).
The DESSIS CAE simulator was used to learn more about ESD mechanisms. The process simulator DIOS was applied to two configurations (with and without a buffer layer) of a basic RF transistor cell as a first analysis step. For the ESD simulation, a HBM circuit was constructed around the physical model, and the capacitor discharge was calculated in the time domain. Since the base-collector path under reverse pulse load was found to be the weakest path, it was used in the analysis. The reference capacitor was loaded to 3000 V with peak current density of about 12.6 mA/µm2 (Fig. 2). In the conventional transistor, a zone of extremely high field is generated at the collectorsubstrate boundary while the field remains much lower in the improved design as a result of the buffer zone. This is due to the fact that the compensating charge for the free electrons of the ESD current is distributed more deeply. A high-strength electric field is also generated around the inner base contact since this is the site of highest current density. Experimental analysis of failed devices in most cases showed melting of silicon at this location.
The current-voltage (I-V) curves of Fig. 3 display the action of the buffer layer. The curves are based on several time steps, with arrows and marks indicating the time flow. The oscillations at the beginning are caused by subsequent ignition of avalanche and voltage breakdown due to the generated free carriers but play no role in the ESD analysis. The device with the buffer layer has an I-V characteristic with positive slope: if the avalanche should "burn" hotter at one spot, a higher voltage would be required for it. Since the voltage is fixed and the same for any spot, however, current crowding is prohibited.
The transfer of production of all discrete RF transistors into Infineon's new self-aligned double poly process also offered the opportunity to produce the new BFP460 design. In this new process, the emitter is formed by depositing an n-poly layer, rather than by implanting arsenic dopant for the emitter in the older processes. The new approach provides tighter control of production process parameters and supports high-volume runs of transistors within narrow ranges of parameter distributions. For example, DC current gain (hFE) of planar RF transistors, which tends to normally scatter over a wide range, can be controlled within a narrow window of 100 to 150 with high yields in BFP460 production.
The BFP460 was used in a wideband feedback LNA for UHF (Fig. 4), although the ESD-hardened transistor is suitable for a wide range of applications. This particular LNA was used to boost the sensitivity and range of receiver RF ICs for RKE and TPMS applications at 315 and 434 MHz. The LNA requires only nine components, including the BFP460 transistor. For reduced cost, no chip coils (inductors) are used, just resistors and capacitors. The application board includes an optional low-cost, lumped-element bandpass filter set to a center frequency of 315 MHz. The filter may be retuned for 434 MHz, and is intended to reduce the effect of out-of-band "blocking" signals on the RKE receiver chain. The application board allows testing of the LNA by itself, the filter by itself, or the cascade of the LNA and filter together.
The LNA is designed for unconditional stability and exhibits good return loss, gain, and noise figure from 300 to 1000 MHz. It can be used at the 315-, 434-, or 900-MHz ISM bands with no changes required (Table 2). Interested readers should contact the author or this magazine for a copy of the Bill of Materials (BOM) for the LNA. Application boards based on the BFP460 are available from Infineon.
|Security Tools Resources|
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