This highly integrated 2.7-GHz source includes all essential DDS circuitry along with a clock driver, divider, high-resolution DAC, and combination phase detector/charge pump.
Direct-digital synthesis (DDS) has long promised precise, agile control of output waveforms, although limited in frequency and often in spurious performance. The AD9956 AgileRFTM DDS from Analog Devices, Inc. (Norwood, MA), however, brings the benefits of DDS technology to an output range reaching 2.7 GHz, providing RF/microwave designers with a high-resolution, programmable signal source capable of sub-Hertz frequency resolution and microscopic current consumption. The high-speed DDS features 48-b tuning resolution, an on-board low-power 14-b digital-to-analog converter (DAC), and flexible, reconfigurable circuitry that can be used for both microwave and high-speed clock generation.
The highly integrated AD9956 incorporates a DDS core, RF divider, DAC, phase detector/charge pump, and differential clock driver (Fig. 1). The design features a 48-b phase accumulator for precise tuning, a 14-b phase offset word to give designers a mechanism of matching system delays, and a 24-b frequency accumulator to provide a method of linearly sweeping between two frequencies. The instantaneous value stored in the phase accumulator represents the instantaneous phase of a sinusoidal frequency. On each system clock cycle the phase accumulator increments by a quantity determined by a value—the frequency-tuning word (FTW)—stored in a control register. The accumulator continues to advance its output value by the FTW until it overflows (i.e., surpasses its maximum value or capacity). A large FTW results in more-frequent overflows, thereby representing a higher frequency. In contrast, a small FTW leads to less-frequency overflows and represents a lower frequency.
The AD9956, with a 48-b phase accumulator, synthesizes a frequency, f0, according to f0 = (Tfs)/248, where fs is the system clock frequency, T is the value of the FTW, and 0 T 247. Any change in the FTW value results in a nearly instantaneous, phase-continuous change in the output frequency. In addition to the 48-b of frequency tuning resolution, a 14-b phase offset register controls the phase of the output in increments of 0.22 deg. The accumulator output increases linearly and cannot directly represent a sinusoidal frequency. As the phase accumulates, the phase-to-amplitude conversion circuit converts the accumulated phase to a 19-b representation of the amplitude of the sinusoid. Following the phase-to-amplitude conversion, the data passes to the DAC for conversion to an analog signal.
Obviously, the 14-b DAC cannot resolve all 48 b of the AD9956's phase accumulator's resolution. Furthermore, converting all 48 b of phase resolution to amplitude information would require a massive, power-hungry digital design. To minimize power consumption and die area, the AD9956 makes use of a subset of the 48-b phase accumulator by only taking the 19 most significant bits (MSBs) and truncating the remaining 29 b before going through the phase-to-amplitude conversion block. The truncation process produces repetitive errors in the digital signal which can show up as spurious content in the output spectrum. However, since the errors are algorithmic in nature, their placement and size are predictable. The magnitude depends on the capacity of the phase accumulator and the number of bits that are truncated. The DAC does not use most of the information contained in the least significant bits (LSBs) of the 48-b accumulator and so truncation generally does not adversely impact performance. The 14-b DAC limits the AD9956's overall spurious-free dynamic range (SFDR), and the spurious contributions are not noticeable if after truncation enough phase information remains to keep their energy below the DAC harmonics.
The AD9956 can also execute multichip synchronization and perform linear frequency sweeps thanks to its 24-b frequency accumulator. By programming start and stop frequencies into the AD9956 along with a step size (the delta FTW), the device can be made to ramp from start to stop frequencies in a linear fashion. The process is controlled externally by changing the state of the PS<0> pin from low to high. Clock generation represents one potential application of the AD9956, so a clock output that coincides with its system clock has been provided to help designers synchronize its signal to other devices in their systems.
The reduced power DDS architecture of the AD9956 includes an important new feature with the addition of an RF divider at the clock input pins. The user applies a reference clock for the DDS and DAC at this divider port. Differential inputs are provided and are internally biased for ease of use. The input reference is the supply rail and provides a 1 V common-mode input range. A simple arrangement would require only AC coupling and the application of a reference clock source. Maximum input frequencies to 2.7 GHz are possible as the divider will bring the reference clock down to the DAC and DDS sample clock rate. The usable system clock frequencies fall in the range of 1 to 400 MHz. The RF divider is a programmable 3-b modulus-2 divider capable of dividing the input 2, 4, or 8 times, generating a low-phase-noise system clock for the chip. The AD9956's integrated DAC provides a 10-mA full-scale current and drives the analog output to about 500-mV pp differential signal when terminated with 25-(omega) resistors. Highlights of the DAC include low power consumption, a 400 MSamples/s update rate, and 14-b resolution. A 1.8-V supply sets the DAC power consumption at 30 mW even while converting data at a 400 MSamples/s rate. The phase noise level is about −125 dBc/Hz offset 1 kHz from the carrier and reaches a noise floor of about −145 dBc/Hz offset 1 MHz from the carrier.
The phase-detector and charge-pump combination provides the necessary components to build a high-speed phase-locked loop (PLL) using voltage-controlled oscillators (VCOs) up to 650 MHz. At the inputs to the phase detector, programmable dividers divide incoming frequencies down to the maximum update rate of the charge pump and phase detector (160 MHz). Dividers at both the reference input and the oscillator feedback input are programmable in integer steps from 2 to 16 and may be bypassed when not needed. The charge-pump/phase-detector combination produces small spurs in the output spectrum at the reference frequency update rate, but since the phase detector operates at such a high a maximum rate, these spurious signals move well outside the PLL's closed-loop bandwidth where the filter greatly reduces their magnitude. The charge pump's maximum output current, which is programmable in 0.5-mA steps, is 4 mA. The high degree of programmability offered in the PLL components adds flexibility eases the task of optimization in the loop design process. Additionally, the AD9956 reduces the cost of generating a loop reference frequency by means of an on-chip oscillator that accepts 20-to-30-MHz crystals. Used in conjunction with the PLL components, the oscillator block offers a low-cost solution for the loop reference.
A 2.4-GHz VCO provides the clock input and the RF divider scales the VCO frequency by 1/8 to provide a system clock to the DDS and DAC. A filter reconstructs the DAC output which then feeds back to the phase-detector oscillator input where the phase detector compares it with the reference frequency. Reference signals can be generated by external sources to 650 MHz or by using a low-cost crystal in the 25-MHz range with the AD9956's on-board oscillator.
In addition to being a microwave synthesizer, the AD9956 also serves as a high-speed precision clock generator. With its precise tuning and ability to control phase accurately, a DDS makes an excellent clock source. Unfortunately, a traditional DDS is limited to output frequencies below one-half of the system clock rate due to the Nyquist criterion. However, since the AD9956 is actually a hybrid oscillator, with DDS circuitry, a PLL, and a clock driver, it overcomes the classic Nyquist limitation and can generate low-jitter clock signals to 650 MHz. The AD9956's high-frequency clock driver circuit generates differential clock signals with PECL output levels when terminated with a standard PECL termination arrangement. The configurable input operates to 650 MHz and drives a 50-(omega) transmission line plus a 5-pF capacitance. Three configurations are available for driving the output, including configurations in which the phase-detector feedback input drives the clock output and in which the RF divider input or output drives the clock output.
Since clock jitter can limit the performance of a clocked analog-to-digital converter (ADC), the AD9956 was used to clock the AD6645 14-b ADC in laboratory tests. Using a low-cost 25-MHz crystal as the reference oscillator and putting the DDS in the PLL feedback loop, the AD9956 generated a 100-MHz clock to encode a 170-MHz analog signal. The measured signal-to-noise ratio (SNR) during the conversion was about −63 dBc, corresponding to less than 0.4 ps root-mean-square (RMS) clock jitter.
The AD9956's different circuit blocks can be configured in numerous ways to yield different circuit configurations. While it is beyond the scope of this article to discuss this list exhaustively, four circuits will be covered. The first is a "fractional-divide" loop. Traditional PLL circuits have suffered from two fundamental limitations. First, because the dividers in the feedback path had integer values, the resolution of the loop was limited. Second, since a simple divider was used in the feedback path, the gain of the loop was static, limiting the ability to sweep the output frequency. Since the AD9956 can be used with the DDS portion of the chip in the feedback path of the PLL (Fig. 2), the two traditional PLL limitations can be overcome. For one thing, the DDS is capable of fractional division. The VCO, operating up to 2.7 GHz, is fed to the RF divider of the device. The divided output, typically in the range of about 300 MSamples/s, serves as the system clock for the DDS. The DDS can then generate 248 different frequencies from this clock, with 10-µHz tuning resolution. Because the DDS offers a linear sweep function, the divide value can be programmed to change over time, offering a linearized sweep of the VCO output. The sweeping profile can be configured by adjusting both the incremental frequency step size and the incremental frequency step rate.
It should be noted that since the ramping occurs in the feedback path, the VCO output will actually follow a 1/x(t) relationship, which is not truly linear. For any practical VCO with sufficient Q factor, the tuning range will be restricted to a region where this can be approximated as a very linearized response. In Fig. 3, a sweep is shown across a 35-MHz range and the covariance of the VCO output with a truly linear function is 0.995. A 35-MHz sweep at this intermediate frequency (IF) corresponds to a 4.29-GHz sweep at the transmitter. As an additional convenience feature, the reference input of the AD9956's PLL includes an oscillator circuit allowing the use of a low-cost but stable 25-MHz crystal. This swept function can be useful in a variety of military and automotive radar systems, such as vehicular systems using adaptive cruise control.
The second example circuit is oriented more toward network clocking applications. In an application such as this, the DDS is again used in the PLL feedback path to provide precision tuning. However, the VCO output is fed to the RF divider input and is also routed to an on-chip clock driver (Fig. 4). The clock driver is a squaring device capable of operating to 650 MHz, so the VCO output must be kept at or below this rate in this configuration. The clock driver is actually a current output device, but when driving transmission lines terminated in 100-(omega) impedances, a PECL voltage swing will be seen at the load (0.9 to 1.6 V). If a higher-frequency VCO is to be used, an external RF divider can be inserted into the feedback path to keep the clock driver input at or below 650 MHz. As with the first circuit, the oscillator section of the reference input of the PLL is enabled, allowing for the use of an inexpensive yet stable crystal as a reference frequency source. Because the DDS is capable of 48-b tuning, the frequency resolution of the output clock is about 4 (Hz)0.5 (for a 400 MSamples/s clock). Preliminary investigation of the jitter on the clock driver, PLL and DDS indicate that the jitter in this loop is approximately 0.5 ps RMS. With its ability to provide clock signals to 650 MHz, the AD9956 is capable of clocking optical channels up to the OC-48 rate of 622 MHz.
The third example uses the DDS and the PLL separately (Fig. 5). The PLL is configured more like a traditional PLL, using the included RF divider and the phase-detector divider to generate the frequency gain for the loop. The VCO operates at 2.4 GHz. This signal is fed to the RF divider and divided by 8, leaving a signal of 300 MHz. This signal is routed to the clock driver, which is externally connected to the feedback input (OSC) of the phase detector. The oscillator input has its own divider which can take divider values from 1 to 16. Placing the divider at 15 sets the phase-detector frequency at 20 MHz. The loop employs a 20-MHz crystal for the reference frequency. The 2.4 GHz tone is sent to the LO input of an external passive mixer. The 300-MHz signal also acts as the clock for the DDS. The DDS can be programmed with eight different frequency tuning words or eight different phase offset values, allowing for eight-state frequency-shift-keying (8FSK) or eight-state phase-shift-keying (8PSK) modulation. The DDS modulated output, which can be to 120 MHz, and can have a modulation rate of to 75 MHz, is fed to the IF input of the passive mixer. The result, after external filtering, is a low-cost ISM-band modulator capable of 8PSK or 8FSK to 2500 MHz, with modulation rates to 75 MHz.
Finally, the AD9956 can be configured to generate a different sort of clocking circuit. Many transceiver architectures employ an analog-to-digital converter (ADC) and a receive-side-signal-processor (RSSP) which require clock signals at about 100 MHz. The ADC clock must have very low-jitter (less than 1 ps RMS). The RSSP doesn't have the same jitter requirements, but it is very useful to be able to skew the rising edge of this signal with respect to the ADC clock rising edge. By using a 400-MHz voltage-controlled crystal oscillator (VCXO), the DDS and the RF divider can be employed independently to generate two different 100-MHz clocks with the ability to skew one rising edge with respect to the other with 14-b phase accuracy (Fig. 6).
The low-jitter ADC clock is generated by sending the 400-MHz signal to the RF divider and sending the divided-by-four output to the clock driver. The undivided 400-MHz signal is also used to clock the DDS, which is also set to divide by four. The DDS has a 14-b phase offset word which can be used to adjust the rising edge of the RSSP clock signal with respect to the ADC clock. At 100 MHz, the skew resolution of this signal is 0.6 ps. Because only one clock driver is included on-chip on the AD9956, a second, external comparator would be required to square the output of the DDS. P&A: $20 (1000 qty.); 60 days.