If it is true that one day the last shall be first, then the designers at IceFyre Semiconductor (Kanata, Ontario, Canada) have an edge. The company, a relatively late entrant in the race for wireless-local-area-network (WLAN) market share, has joined the competition in a big way, sampling its high-performance SureFyre™ 802.11a and TwinFyre™ 802.11a/b/g chip sets with promises of improved power efficiency, range, and sensitivity, particularly for demanding multimedia applications.

Although new to the market, the fabless semiconductor firm boasts a management team with impressive lineages that include IBM, Nortel Networks, National Semiconductor, Intersil, and Nokia, and more than 31 patents granted or pending for a new class of orthogonal-frequency-division-multiplexing (OFDM) radio design. The company's first two integrated-circuit (IC) sets are the SureFyre family, designed to support the 5-GHz IEEE 802.11a standard for bit rates to 54 Mb/s, and the TwinFyre family, which can be used for the three leading WLAN standards, IEEE 802.11a, 802.11b, and 802.11g, at both 2.4 and 5 GHz.

The SureFyre system is comprised of three chips: the ICE5351 802.11a combination baseband processor and RF radio IC, the ICE5125 802.11 general-purpose media-access-controller (MAC) IC, and the ICE5352 power-amplifier (PA) IC. The SureFyre chip set supports WLAN designs from 4.90 to 5.85 GHz using OFDM modulation, and can achieve high transmit power levels (and improved range) with reduced power consumption compared to competing 802.11b solutions. The first two chips are fabricated with an 0.18-µm RFCMOS silicon process while the PA is fabricated with GaAs. The chips combine to achieve more than 200 mW transmitter average RMS output power and receiver sensitivity that exceeds the 802.11a standard by as much as 10 dB. The system error-vector-magnitude (EVM) performance is 2 dB better than the 802.11a requirement, and the system-level noise figure is less than 8 dB. System power consumption is extremely low at 1015 mW for 100 mW EIPR. Of note for multimedia system designers, the delay spread for the SureFyre system is an almost-negligible 150 ns.

The chip set's individual components include the ICE5351, which combines low-power differential RF circuitry and the digital baseband architecture on the same device. The integrated partitioning is well suited for support of proprietary MACs and embedded host-based MAC platforms, in contrast to the limitations of chips that integrate a baseband processor with the MAC. The ICE5351 can handle data rates of 6, 9, 12, 18, 24, 36, 48, and 54 Mb/s. It employs unique algorithms to limit the peak-to-average power ratio (PAPR) of OFDM signals (maintaining a constant amplitude envelope) for maximum efficiency when used with the ICE5352 PA. Its receiver architecture does not require an external intermediate-frequency (IF) filter or baseband filter components, yet achieves receive sensitivity is −89 dBm at 6 Mb/s and −70 dBm at 54 Mb/s. The ICE5351 includes an automatic-gain-control (AGC) circuit with 0-to-70-dB range, and a transmit-power-control range of better than 20 dB. The nique AGC circuitry is capable of settling in a few short symbols, giving the receiver unprecedented response time and enhanced efficiency. The IC shaves peak transmit power consumption to less than 570 mW and achieves transmit EVM of −27 dB at all data rates and output power levels. The ICE5351 is supplied in a 15 × 15 × 1.6-mm low-profile fine-pitch ball-grid-array (LFBGA) housing.

The ICE5125 802.11 MAC is compliant with 802.11a, b, and g standards. The IC includes a 32-b bus master DMA controller to transfer data to and from the system memory, minimizing the load on the host central-processing unit (CPU). The MAC supports a variety of security methods as well as 64- and 128-b encryption keys. For 802.11a/g, it support data rates of 6, 9, 12, 18, 24, 36, 48, and 54 Mb/s, while for 802.11b, it supports data rates of 1.0,2.5, 5.0, and 11.0 Mb/s. It supports automatic rate switching to adapt to different link conditions. It features on-chip packet buffers, supports dynamic frequency selection and transmit-power-control functions, and includes Windows 2000, Windows XP, and Linux 2.4 drivers. The ICE5125 is supplied in a 12 × 12 × 1.4-mm LFBGA housing.

The cornerstone of the SureFyre collection, the ICE5352 gallium-arsenide (GaAs) pseudomorphic-high-electron-mobility-transistor (PHEMT) amplifier is optimized for use from 5.15 to 5.35 GHz and is first in a family of PAs covering the global 4.9-to-5.85-GHz band. It is unique among WLAN PAs, employing efficient Class F switch-mode technology along with patented low-loss Chireix signal combiners (see figure). The result of this novel technology is an amplifier capable of delivering 125 mW (+21 dBm) output power with 35-percent power-added-efficiency (PAE) for IEEE 802.11a applications, or 200 mW (+23 dBm) output power with 31-percent PAE. The amplifier can provide continuously variable output-power levels from +2 to +23 dBm (by varying the DC supply voltage from +0.5 to +7.0 VDC), and achieves system-level transmit modulation accuracy (EVM performance) of −27 dB at a data rate of 54 Mb/s. The amplifier consumes only 360 mW power when generating +21 dBm output power and only 250 mW power when generating +19 dBm output power. The ICE5352 PA is supplied in an 8 × 8-mm, 15-pin ceramic-leadless-chip-carrier (CLCC) package.

For developers working on multiple-WLAN-standard solutions, the TwinFyre™ 802.11a/b/g system handles the three leading WLAN standards at both 2.4 and 5 GHz. The chip set consists of the ICE2501 802.11b/g RF IC, the ICE5825 802.11a IC with baseband processor, the ICE5125 802.11 MAC, and the ICE5352 PA. The system is ideal for partner-provided commodity 2.4-GHz radios and third-party MAC solutions, with strong support for IEEE 802.11b and IEEE 802.11g.

The TwinFyre chip set basically adds 802.1b and 802.11g capabilities to the 802.11a performance of the SureFyre system, with as much as +17 and +22 dBm output power while working in 802.11b and 802.11g operation modes, respectively. The TwinFyre system offers 10 dB better receive sensitivity than the 802.11b/g specifications.

Both the SureFyre and TwinFyre chip sets benefit from innovative technology, including TrueSygnal™ per packet equalization and decode processing, which provides equalization of all carriers in the presence of fading and dynamic-channel-quality assessment to select optimal channels in the presence of interference while optimizing output power levels. Working with a Viterbi decoder, the TrueSygnal approach uses equalization results (channel state information) to optimize the decoding process based on the quality of the receive carrier signals. The IcePick™ per packet antenna diversity provides as much as 10 dB additional gain in receiver sensitivity, especially in multipath environments. Another feature offered is Transmit per Packet Power Control (TPPC), which provides for dynamic interference avoidance, whereby the transmitted power of each OFDM packet is adjusted for optimal AP-STA performance, but minimal RF network interference.

The ICE5351 and ICE5352 ICs are currently available in sample quantities as part of the ICE5300A-EVK evaluation kit, while the ICE5125 is sampling as part of the ICE5100A-EVK evaluation kit. SureFyre-based Mini-PCI reference designs will be available during the last quarter of 2003. The TwinFyre chip set will begin sampling in the second quarter of 2004, with volume production expected by the third quarter of 3004. IceFyre Semiconductor Corp., 300-411 Legget Dr., Kanata, Ontario K2K 3C9, Canada; (613) 599-3000, FAX: (613) 599-4965, Internet: www.IceFyre.com.