Careful modeling and comparison with measurements can show the effects of a low-cost package on MMIC performance, and help guide the MMIC design for best performance.
Traditionally, monolithic microwave integrated circuits (MMICs) have been designed for function and performance, but without much forethought for package options. Packages were often developed after the circuit, and this "second-thought" approach would result in loss of circuit performance. A more practical approach is to perform accurate design of high-frequency MMICs for the package itself, in particular, for fully encapsulated packages. By applying a simple electromagnetic (EM) simulation technique, it is possible to account for the encapsulant's effect on the MMIC's field-effect-transistor (FET) active devices. The article that follows will also explore modeling the MMIC's passive structures as well as the package's interconnection transitions. As an example, a 20-GHz commercial amplifier will be used to demonstrate the effectiveness of designing the circuit for the package.
High-frequency packaged products have become more prevalent in microwave systems in recent years. In the past, very few packaged products operating above 6 GHz existed, while today, packaged product offerings are available for many high frequency functions including amplifiers, mixers, filters, voltage-controlled oscillators (VCOs), and multifunction converters. System designers and component suppliers are driving the shift to packaged MMICs. For the system designer, packaged products increase the ease of handling and assembly, and by lowering product costs with known good functions. For the supplier, packaged parts increase the serviceable available market for products, increase the supplier's value-added service and product revenue, and simplify the sales distribution channel by eliminating many difficulties associated with the handling and storage of die products. The challenge for packaged device manufacturers is to design high-frequency products with acceptable RF performance in the lowest-cost package styles available.
Packages are available in many different styles. Lidded soft-board packages and aircavity packages work well at high frequency, but tend to cost more. In contrast, fully encapsulated standard package designs, such as the quad flatpack no-lead (QFN) package that was originally designed for lower-frequency analog and digital applications, are relatively inexpensive. An encapsulated QFN package has a metal paddle (bottom) to which the die is mounted, typically with epoxy. The die bond pads are then wirebonded to metal leads and the entire assembly is covered (encapsulated) with mold compound. Multiple assemblies are built on a lead frame, then singulated as complete individual packages.
The first low-cost packaging attempts put existing high-frequency MMICs, designed for an open-air environment, into encapsulated QFN packages. Examples include amplifiers, analog attenuators, and passive structures. In all instances, the final packaged product generally performs well despite deleterious effects caused by the presence of the encapsulant over the MMIC. Designers must take note of the fact that device gain, power, and linearity performance degrades due to the changes in die operating environment. The operating frequency band can also shift with environmental variations. Consequently, a MMIC designer's challenge is to accurately simulate the performance of the packaged die from the beginning of the process so that the final product will meet the design's performance goals.
As an example, the model TGA2521-SM MMIC from TriQuint Semiconductor (www.triquint.com) is currently being developed as a point-to-point amplifier covering the 17.7-to-19.7-GHz and 21.2-to-23.6- GHz microwave radio bands. The die is being designed with TriQuint's 0.25-m MMW 3MI pHEMT process and is packaged in a Unisem 4 x 4 16- lead QFN housing (Fig. 1). The special design techniques that account for the encapsulated package environment are detailed.
An important modeling consideration is the transistor performance change that occurs due to die encapsulation. FETs provide transconductance (Gm) with inherent gate-todrain capacitance (Cgd), gate-to-source capacitance (Cgs), and drain-to-source capacitance (Cds). In small-signal models,1-3 these parameters (and others) define the optimum source and drain loads for maximum gain. In nonlinear device models, they define the loads for maximum power and linearity. Traditionally, models are extracted from measurements taken in an open-air (unpackaged) environment. Encapsulant with higher relative permittivity (or dielectric constant, r), in this case r = 4, replaces the air ( r = 1) atop the die. The encapsulant raises the FET capacitances by perturbing the fields between the gate, drain and source.
To model the capacitance shifts, a simple procedure using two-and-onehalf- dimensional (2.5D) EM simulations based on Sonnet Software (www.sonnetusa.com) was developed. In the simulator software, the specific FET structure was built with thick lines, gate fingers, drain fingers, and source air-bridges to accurately simulate the FET's physical structure (Fig. 2). The simulation reference planes were set at the same place as the model reference planes. The simulation was then run twice, once in air and once in encapsulant. The resulting S-parameter responses were then fitted to a simplified model, consisting of only the capacitances Cgd, Cgs, and Cds (Fig. 3). The openair capacitances were fit first. For the encapsulant fit, Cgs was fixed to the open air value and Cds and Cgd were refit to the EM simulated S-parameters with encapsulant. Cgs was left unchanged because the extracted value for Cgs is small compared the real intrinsic Cgs value. The absolute delta between the two Cds values and the two Cgd values were then added to the full small-signal or nonlinear model parameters to produce the final encapsulant-shifted version (Fig. 4). This technique was verified by comparing the simulated capacitance shifts to measurements of the FET in air and with encapsulant cured on top. In Fig. 5, the measured capacitance shifts for 12 FETs are compared to the simulated shifts. By using simple EM simulations, the MMIC designer can readily obtain the capacitance shifts caused by encapsulant for many physically different transistors.
In the MMIC, electric fields exist both in the GaAs substrate and in the medium above the die. A microstrip line with length of 200 m, width of 20 m, and thickness of 7 m on 100 m thick GaAs ( r = 12.9) can serve as a good example. In air, the line's characteristic impedance is 70 O with an S21 phase of 13.1 deg. at 20 GHz. In encapsulant, the line's characteristic impedance is 62 O with an S21 phase of 14.3 deg. at 20 GHz. The encapsulant increases the line's phase length and decreases the line's impedance. Encapsulant affects the performance of the MMIC's passive components, including the transmission lines, coupled lines, inductors and capacitors. These components establish the impedances presented to the FETs, thereby helping to define the circuit's gain, return loss, noise, power, and linearity performance. The passive components should be accurately simulated in the correct environment to ensure good circuit performance.
For the TGA2521-SM MMIC amplifier design, all passive components, including microstrip lines, Lange couplers, and capacitors, were simulated by means of the EM simulation software. All components were simulated with 100-m GaAs substrate with relative dielectric constant ( r) of 12.9 and encapsulant with 0.47-mm thickness ( r = 4) above the die. At the completion of the design, the simulation consisted of the shifted FET models surrounded by EM simulated S-parameter files.
The package transition from the die to the board was examined using the High-Frequency Structure Simulator (HFSS) three-dimension (3D) EM simulator from Ansoft Corp. (www.ansoft.com). The transition included the bond wires, package lead, and printed-circuit-board (PCB) microstrip. A procedure further characterizing the transition was also developed. In developing the simulation procedures, it was determined that the full package measurement equals the input transition plus the die measurement (with encapsulant) plus the output transition. First, a package's S-parameters (with die) were measured. Then, the encapsulant was cured atop a die in an open-top package while leaving the on-chip RF input and output pads exposed. The die's S-parameters were measured by probing directly onto the chip. The 3D simulation of the transition was verified by comparing the full package measurement to the combination of the simulated transition on the input, plus the measured die, plus the simulated transition on the output. To ensure low return loss, a tuning circuit on-chip compensated for the package transition's parasitic response. Figures 8 and 9 show the return-loss performance.
An MMIC designer should consider die temperature to assure adequate reliability. For example, a typical PCB carrying the package heats to a maximum +80C under worst-case operating conditions. The 8-mil-thick copper alloy package paddle adds +3C thermal rise while the high-thermalconductivity epoxy adds another +3C thermal rise. The 100-m-thick GaAs substrate contributes an additional +43C thermal rise under the FET that is at the highest typical operating temperature. With a worst-case channel temperature of +129C, the MMIC's median lifetime is greater than 800 years. Circuit-board design, choice of epoxy, and FET thermal design are important product lifetime considerations and must be consistent with system- application requirements.
Several design considerations influenced the physical dimensions of the die inside the package. To minimize parasitic bond wire inductance in the RF path, the die horizontal dimension was lengthened to shorten the RF bond wires. The die vertical dimension was decreased to minimize die size. However, by minimizing the die size, the DC bond wire lengths increased to approximately 1 mm (about 0.8 nH). The increased DC bond wire inductance can cause insufficient bypassing in the 100-MHz-to-1-GHz frequency range. This is the frequency range below the efficacy of on-chip bypassing, but above the frequency where the first out-of-package bypass capacitor is effective through the bond wire inductance. A representative 3D model of the DC package lead, the bond wire inductance, the on-chip bond pad and the microstrip line to the out-of-package capacitors were all simulated. The circuit's outof- package capacitors consisted of equivalent RLC models. Loop-gain analysis4 performed on all FETs ensured stability.
The S-parameters of the measured package matched the simulated sparameters well. Figure 7 shows the simulated gain and the measured gain. The reference planes for the measurements are on the PCB 0.9 mm from the package edge. The TGA2521- SM die in open-air was also measured and can be seen with the package measurement in Fig. 6. The band shift and gain change are due to the encapsulant's effect on the matching networks and FETs. Figures 8 and 9 show good return-loss performance due to the package transition characterization and tuning network. In addition to good small-signal performance, the TGA2521-SM is designed to produce greater than +20.5-dBm output power at 1-dB gain compression, greater than +31 dBm third-order intercept when measured at +4.5 dBm per test tone, and greater than 14.5-dB gain control.
In summary, this report has detailed special MMIC design techniques that compensate for the environment presented by an encapsulated package. A simple method for modeling the effects of encapsulant on active FET devices improves the accuracy of the active models. The encapsulant changes the performance of the passive structures and the package transition affects return losses. Other considerations, such as the thermal budget, can affect the design of the die and package, especially for devices with high power dissipation. These techniques are now being used effectively in the MMIC design process and will become more important as the market for high-frequency packaged MMICs increases.
1. Michael J. Golio, Microwave MESFETs and HEMTs, Artech House, Norwood, MA, 1991, pp. 207 - 237.
2. Dambrine Gilles, Alain Cappy, Frederick Heliodore, and Edouard Playez, "A New Method for Determining the FET Small-Signal Equivalent Circuit," IEEE Transactions on Microwave Theory & Techniques, Vol. MTT-36, No. 7, 1988, pp. 11151-1159.
3. R. Anholt and S. Swirhun, "Equivalent-Circuit Parameter Extraction for Cold GaAs MESFETs," IEEE Transactions on Microwave Theory & Techniques, Vol. MTT-39, No. 7, 1991, pp. 1243-1247.
4. Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, New York, 1977, pp. 599-607.