Parasitic circuit elements can result from closely spaced inductors and circuit traces, and a variety of other issues when designing circuit layouts for ISM-frequency-band products.

Designing circuits for low-cost products at Industrial-Scientific-Medical (ISM) band frequencies has been greatly simpliflied by the availability of reliable integrated circuits (ICs) that provide many of the transceiver functions. But even the best ICs can be undone by flawed printed-circuit boards (PCBs), although most PCB problems can be avoided by careful design and planning. What follows is a roadmap to guide designers past PCB design oversights, with strategies based on a two-layer PCB using a 0.0625-in.-thick FR-4 substrate. For the examples, most of the operating frequencies range from 315 to 915 MHz, with transmit and receive power levels in the range of -120 to +13 dBm.

Most PCB problems derive from one of a few common causes (**see table**). Mutual inductance is present when two inductors (even two printed-circuit traces) are close together. Current in the first circuit induces a magnetic field that stimulates current in the second circuit (**Fig. 1**). This process is similar to the action between primary and secondary windings in a transformer. When the two currents interact through the magnetic field, the resulting voltage is governed by the mutual inductance, LM:

Y_{B}(V) = L_{M}(dI_{A}/dt)

where

Y_{B} = the injected error voltage in circuit B and

I_{A} = the forcing current in circuit A.^{1}

The value of L_{M} is highly sensitive to the distance between circuits, to the loop areas of the inductors (i.e., the magnetic flux), and to the orientation of the loops. The best tradeoff between circuit compactness and reduced coupling is to properly orient all of the inductors.

An optimal orientation positions circuit B so the plane of its current loop is parallel to the field lines of circuit A. This can be done by orienting the inductors orthogonally whenever possible. As an example, in the model MAX7042EVKIT evaluation kit for a low-power FSK superheterodyne receiver from Maxim Integrated Products, the three inductors on the board (L1, L2, and L3) are in proximity, and so are oriented at 0, 45, and 90 to minimize their mutual inductance (**Fig. 2**).

Just as inductor orientation can affect coupling caused by magnetic fields, too-close placement of circuit traces can act in a similar fashion, leading to mutual inductance between traces. Mutual inductance can degrade the performance of sensitive portions of an RF circuit, such as the input matching network, the tank circuit in a receiver, and the antenna matching network in a transmitter.

Routing a return current path close to the primary current path minimizes the radiated magnetic field. Such layouts also reduce the area of the circuit loop. The ideal low-impedance path for return currents is usually a ground plane under the tracea placement that effectively limits loop area to the thickness of the dielectric times the length of the trace. A split ground, on the other hand, increases the loop area (**Fig. 3**). For traces passing over the split, the return current is forced to follow a higher-impedance path that effectively increases the area of the current loop. This layout also makes the trace more susceptible to the effects of mutual inductance.

As with physical inductors, the orientation of the traces plays a role in the coupling of magnetic fields. If it becomes necessary to run traces from sensitive circuits close to each other, it is preferable to run them in orthogonal directions to reduce coupling (**Fig. 4**). If that is not possible, a guard trace may be needed.

The primary cause of RF layout problems can usually be traced to nonideal circuit properties related to components, as well as their interconnections. Thin traces act as inductive wires, and a trace running over a copper plane or next to other traces forms a distributed capacitance with those structures. When it runs through a via, it tends to exhibit both inductive and capacitive properties.

Via capacitance comes primarily from the coplanar copper of the via pad and the ground plane, which are separated by a relatively small clearance ring. Secondary effects come from the cylindrical copper of the plated through hole (PTH). The effect of parasitic capacitance is typically small, and usually causes only a slight degradation of signal edges in high-speed digital lines, or else a slight shift in the expected frequency of resonant circuits.

The largest parasitic impact from vias is simply the nonideal inductance exhibited by all interconnects. Because most plated-through hole structures in RF PCB designs tend to be the same size as lumped elements, a simple equation can estimate the influence of a circuit via **Fig. 5**:

L_{via} (nH) = 5.08

where

L_{via} = the lumped inductance of the via,

h = the length of the via in inches, and

d = the diameter of the via in inches.^{2}

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Parasitic inductance often has the greatest influence on bypass-capacitor connections. An ideal bypass capacitor provides a high-frequency short between power and ground planes, but nonideal vias reduce the low-inductance properties of both ground and power planes. The value of a typical PCB via (d = 10 mils, h = 62.5 mils) is about 1.34 nH. Given the operating frequencies of ISM products, vias can therefore cause unwanted effects in sensitive blocks such as tank circuits, filter blocks, and matching networks.

Other problems arise when ground vias are shared between sensitive portions of a circuit, such as the two legs of a p network. If an ideal via is replaced with an equivalent lumped-element inductor, the schematic diagram for that circuit will look considerably different (**Fig. 6**). Like the crosstalk from shared current paths,^{3} the resulting increase in shared mutual inductance can greatly amplify crosstalk and feedthrough. In sensitive circuits, the inductance of vias should always be modeled to predict any unforeseen effects. Isolated vias should be used for separate portions of a filter or matching network. The use of thinner PCB substrates will reduce the influence of parasitic inductance from vias.

For ISM-band circuits, the high-frequency input and output lines should be kept as short as possible to minimize loss and radiation. Such loss is typically due to nonideal parasitic properties of the interconnections. Parasitic inductance and capacitance can both influence these circuit layouts, and they are best avoided by using short trace lengths. In general, a 10-mil-wide PCB trace, separated from the ground plane by 0.0625 inches of FR-4 dielectric, has about 19 nH/in. of inductance and 1 pF/in. of capacitance. For an LNA/mixer circuit that includes a 20-nH inductor and 3-pF capacitor, the proximity of circuit and device can greatly influence the effective component values.

Document IPC-D-317A from the Institute for Printed Circuits (IPC)^{4} provides an industry-standard equation for estimating various impedance parameters of a microstrip PCB trace. That document was superseded in 2003 by IPC-22515, which provides more accurate calculations for various PCB traces. Online calculators are available from various sources, most of which base their equations on those found in IPC-2251. A useful reference for PCB trace-impedance calculations is available from the Missouri University of Science and Technology's Electromagnetic Compatibility Laboratory.^{6}

The standard equation for calculating the impedance of a microstrip trace is

Z_{0} (Ω) = r + 1.41)^{0.5}>{ln}

where

e_{r} = the permittivity of the dielectric substrate,

h = the trace height above the ground,

w = the trace width, and

t = the trace thickness (**Fig. 7**).

This formula produces reasonably accurate results for w/h values between 0.1 and 2.0, and er values between 1 and 15. ^{7}

To estimate the effect of trace lengths, it is more useful to determine the detuning effect of trace parasitics on an ideal circuit. In this case we are concerned with stray capacitance and inductance. The standard equation for the characteristic capacitance of a microstrip trace is

C0 (pF/in.) = r + 1.41)>/{ln}

Likewise, the characteristic inductance from the equation, Z_{0} = (L_{0}/C_{0})^{0.5}, can be calculated using results from the previous equations:

L_{0} (nH/in.) = 0.001Z_{0}^{2}(C_{0})

As an example, consider a PCB 0.0625 inches thick (h = 62.5 mils) with 1-oz. copper traces (t = 1.35 mils) 0.01 in. wide (w = 10 mils) over FR-4 material. Note that the relative permittivity, er, for FR-4 is typically 4.35 F/m, but it can range from 4.0 to 4.7 F/m. The characteristic values calculated for this example are Z_{0} = 134 Ω, C_{0} = 1.04 pF/in., and L_{0} = 18.7 nH/in.

ISM-band layouts may have trace lengths of 12.7 mm (0.5 in.) or longer. A trace of that length adds parasitic elements of 0.5 pF and 9.3 nH to a circuit (**Fig. 8**). Such parasitic contributions can cause inductive-capacitive (LC) resonator frequency variations close to 2% at 315 MHz and 3.5% at 433.92 MHz. Effectively, a 315-MHz tank circuit can peak at 312.17 MHz and a 433.92-MHz tank circuit can peak at 426.61 MHz.

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As another example, the recommended component values for a tank circuit in a MAX7042 superheterodyne receiver from Maxim are 1.2 pF and 30 nH at 315 MHz, or 0 pF and 16 nH at 433.92 MHz. Using the equation for tank circuit oscillation,

f_{0} (Hz) = 1/0.5>

it is possible to calculate that the 315-MHz tank-circuit values implemented for the evaluation kit PCB for this receiver already incorporate package and layout parasitic capacitances of about 7.3 and 7.5 pF, respectively. In this example, the LC product is expressed as a lumped capacitance.

A ground or power plane defines a common reference voltage and provides that voltage to all parts of the system through a low-impedance connection. In doing so, the plane equalizes any electric fields and acts as a good shielding mechanism.

DC currents always follow the path of least resistance. Similarly, high-frequency currents always follow the path of least impedance. Thus, for a standard PCB microstrip trace over a ground plane, the return current tries to flow in the area of ground plane just below the trace itself. Interrupting a ground plane can induce various forms of noise, thereby increasing crosstalk effects through magnetic coupling or by concentrating the current (**Fig. 9**).

When a continuous ground is difficult to implement, or shielding is needed, copper pours (guard traces) are typically used (**Fig. 10**). The shielding effect of these traces can be enhanced by tying it to ground at both ends and at multiple locations along its length (i.e., via "stitching").^{8} However, guard traces should not be mixed with traces intentionally designed to provide return currents, since it can cause unwanted crosstalk.

Not grounding a copper pour or tying it to ground at only one end can have limited benefit. In some cases, it creates parasitic capacitance that can change the impedance of nearby traces or act as an unwanted path between portions of a circuit. PCB manufacturers are sometimes asked to add noncircuit copper to a PCB to ensure a consistent electroplating thickness. These floating copper areas should be avoided, however, because they can interfere with the schematic design.

The effect of any ground plane must be taken into consideration near an antenna. Any monopole antenna will regard ground planes, traces, and vias as parts of the counterpoise, and nonideal counterpoise shapes can influence the antenna's radiation efficiency and directionality (radiation pattern). A ground plane, therefore, should not be placed directly under a monopole PCB trace antenna.

In the case of a crystal oscillator, parasitic capacitance can pull the oscillator's operating frequency.^{9} To avoid such an event, any stray capacitance on the crystal leads, solder pads, traces, or the connection to an RF device should be minimized. Short traces should be used between the crystal resonator and the active RF device. Interconnect traces should be separated as much as possible. And the ground plane under the crystal should be vacated when shunt capacitance is thought to be excessive.

Planar trace or PCB spiral inductors should be avoided in ISM-band circuits. The inaccuracies inherent to a typical PCB manufacturing process, such as the width and space tolerances, can greatly affect accuracy of the component value. As a rule, the most controlled and highest-Q inductors are wire wound types. Next in quality are the ceramic-layer inductors typically manufactured by the same companies that produce ceramic multilayer chip capacitors. Nevertheless, some designers must use to a spiral trace inductor as a last resort. The standard for calculating the inductance of a planar spiral inductor comes from the classic Wheeler equation:^{10}

L (H) = (a^{2}n^{2})/(8a +11c)

where

a = the average radius of the coil in inches,

n = the number of turns, and

c = the width of the winding core (r_{Outer} r_{Inner}) in inches.

For coils with c > 0.2a^{11}, this calculation is accurate to within 5%.

Many modifications apply when using square, hexagonal, and other shapes for producing a single-layer spiral inductor. A good approximation has been developed for modeling planar inductors on integrated circuit wafers. For that purpose, a modified version of the standard Wheeler equation works well for small geometries and square dimensions:^{12}

L_{MW} (H) = K_{1}_{0}2d_{avg})/(1 + K_{2}?)> where

? = the fill ratio, ? = (d_{out} d_{in})/(d_{out} +d_{in}),

n = the number of turns,

d_{avg}= the average diameter, d_{avg}= (d_{out} d_{in})/^{2}, and

K_{1} = 2.36 and K_{2} = 2.7513 for a square spiral.

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The reasons to avoid this form of inductor are numerous. They are typically limited to low-inductance values due to space constraints, but the most critical reason to avoid trace inductors is that their small geometry and poor control of critical dimensions often results in an unpredictable inductance value. These unpredictable values, of course, will account for differences between modeled and measured results. Other reasons to avoid these PC inductors are a lack of testability by the PCB fabricator for actual inductance values and a tendency for the inductor to couple noise to other parts of the circuit.

In summary, avoid the use planar trace inductors and use wire-wound inductors whenever possible.

REFERENCES

1. Howard Johnson and Martin Graham, Martin, Eds., High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, Englewood Cliffs, NJ, 1993, p. 29.

2. Howard Johnson and Martin Graham, Martin, Eds., High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, Englewood Cliffs, NJ, 1993, p. 258.

3. Howard Johnson and Martin Graham, Martin, Eds., High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, Englewood Cliffs, NJ, 1993, p. 247.

4. Institute for Interconnecting and Packaging Electronic Circuits or Institute for Printed Circuits, www.ipc.org.

5. IPC-2251 Design Guide for the Packaging of High Speed Electronic Circuits, High Speed/High Frequency Committee (D-20) of IPC, November 2003.

6. Missouri University of Science and Technology's Electromagnetic Compatibility Laboratory emclab.mst.edu/pcbtlc2/index.html, PCB Trace Impedance Calculator.

7. Howard Johnson and Martin Graham, Martin, Eds., High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, Englewood Cliffs, NJ, 1993, p. 187.

8. Howard Johnson and Martin Graham, Martin, Eds., High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, Englewood Cliffs, NJ, 1993, p. 201.

9. "How to Choose a Quartz Crystal Oscillator for the MAX1470 Superheterodyne Receiver," Application Note 1017, Maxim Integrated Products, March 2002, pp. 2-4.

10. Harold A. Wheeler, Simple Inductance Formulas for Radio Coils, Proceedings of the Institute of Radio Engineers, Vol. 16, No. 10, October 1928, pp. 1398-1400.

11. Missouri University of Science and Technology's Electromagnetic Compatibility Laboratory emclab.mst.edu/pcbtlc2/index.html, PCB Trace Impedance Calculator.

12. Sunderarajan S. Mohan, Hershenson, Boyd, and Lee, IEEE Journal of Solid-State Circuits, Vol. 34, No. 10, October 1999, pp. 1419-1424.

13. Sunderarajan S. Mohan, Hershenson, Boyd, and Lee, IEEE Journal of Solid-State Circuits, Vol. 34, No. 10, October 1999, p. 1420.