Scientists Demonstrate Wafer-Scale Graphene-On-Silicon Technology

Nov. 17, 2009
MALIBU, CA HRL scientists have fabricated and demonstrated graphene- on-silicon field-effect transistors (FETs) at full wafer scale. This work is part of the Carbon Electronics for RF Applications (CERA) program, which is sponsored by the Defense ...

MALIBU, CA HRL scientists have fabricated and demonstrated graphene- on-silicon field-effect transistors (FETs) at full wafer scale. This work is part of the Carbon Electronics for RF Applications (CERA) program, which is sponsored by the Defense Advanced Research Projects Agency (DARPA) and under the management of the Space and Naval Warfare Systems Center.

CERA's goal is to exploit the unique physical characteristics of graphene to create electronic components that will provide game-changing enhancements to imaging, radar, and high-bandwidth communications applications. Such enhancements have been hindered by component cost, limited resolution, and high power dissipation.

Graphene, which is a single layer of carbon atoms densely packed in a tight, honeycomb crystalline lattice configuration, boasts extremely high current-carrying capacity, excellent thermal conductivity, and low-voltage operation. The challenge was to integrate graphene onto a silicon platform to reap the benefits provided by the material. The demonstration of silicon-on-graphene brings the team one step closer to meeting CERA's goals. HRL has been collaborating with universities, commercial companies, and the Naval Research Laboratory on this program.

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