This two-stage LDMOS-based RFIC provides the benefits of a high-linearity driver stage with the 25-W output power of a final output stage for 3.3-to-3.8-GHz WiMAX applications.
Power amplifiers (PAs) for modern communications systems are generally designed by cascading and paralleling multiple RF transistors to achieve the required solid-state gain and power. With their wide range of impedancematching, optimization, and architectural options, single-stage discrete RF transistors offer a great deal of flexibility for power-amplifier designers, although with some loss of printedcircuit- board (PCB) space compared to RF integrated circuits (RFICs). An optimum solution is the use of an RFIC with adequate output power to satisfy modern communications transmitter requirements.1 A power-amplifier RFIC has been developed based on silicon LDMOS technology with sufficient power to meet 3.8-GHz WiMAX requirements with better than 15-percent efficiency in a final-stage PA application and excellent linearity for driver applications.
The RFIC is the model MW7IC3825N/NB designed and developed with Freescale Semiconductor's high-voltage, seventh-generation (HV7) RF LDMOS process technology. The two-stage RFIC was divided into driver and output stages. It began with the selection of the best unit gate width for maximum gain and frequency response, determined through measurements and computer-aided-engineering (CAE) simulations. To distribute and dissipate heat, the final stage was split into four active blocks and the driver into two active blocks. Considering that WiMAX base station systems require power amplifiers with high output power, low distortion and high efficiency the driver stage was designed to work at maximum efficiency while the final stage was designed to function with the best tradeoff between power and efficiency to minimize driver stage DC power consumption (Fig. 1).
One critical aspect of this design has been to carefully optimize the output pre-matching network. It is essential to add this type of network to increase the output impedance high enough and allow an easy matching of the device. Positioning this circuit as close as possible to the final stage drain is essential to obtain broadband performance because LDMOS-based power transistors have significantly low impedances with a relatively high quality factor (Q). The output impedance can be as low as 100 mohms with a Q as high as 6. Consequently, the output matching network quality is dependant upon how this low and high Q output impedance is transformed.
The most efficient first matching network cell, starting from the final stage output impedance, is a shunt inductance (parallel inductance L1 connected directly between the final stage's drain and the ground through large-valued capacitor C to block DC from the drain DC supply) (Fig. 2). This helps compensate for the output drain-source capacitance (Cds) inherent in every LDMOS field-effect transistor. Therefore, the capacitive output impedance is moved toward the real axis of the Smith chart on a constant conductance circle. In addition, inductive series wires (L2) are added to connect the final stage's drain to the package output lead. This moves the impedance toward the inductive region of the Smith chart on a constant resistance circle. Figure 3 shows a realization of this type of network.
Having such an arrangement causes some presence of mutual inductance (M) between shunt inductor L1 and series inductor L2. Figure 4 shows how M changes the impedance transformation mechanism. It shows two impedance transformations with and without mutual coupling from the final stage's drain to the package lead reference plan. In the ideal case (M = 0), the impedance transformation is optimal. But in a real implementation, the presence of mutual inductance (M > 0) changes the impedance transformation, causing the prematched output impedance (at the package lead reference plan) to be lower. As a result, the prematching network is less efficient in increasing the output impedance.
It is critical to determine this mutual inductance value during the design phase. The output wire-bond array can be optimized in order to minimize mutual coupling while achieving the targeted inductance values for proper impedance matching. In this design, the output pre-matching network was simulated by means of high-frequency structure simulator (HFSS) electromagnetic (EM) simulation software from Ansoft (www.ansoft.com). The CAE software was used to accurately determine the inductance of the wires along with the series resistance and mutual inductance between them. Table 1 shows the importance of using accurate simulation, as it compares values for output prematching extracted with an equation-based tool and an EM simulator. Note that the prematch networks have been loaded with the same impedance. The mutual coupling determined by the equationbased tool differs only by 10 percent from the values given by the EM simulation. The difference in coupling, however, yields significant differences in the final amplifier performance, of 0.9 dB in the output power at 1-dB compression (P1dB), for example.
The MW7IC3825N/NB LDMOS RFIC is designed into an over-moldedplastic (OMP) package. These packages offer a significant cost advantage over traditional air-cavity packages. The OMP package is built utilizing an automatic lead-frame assembly process, and the materials used (copper and plastic) are relatively low in cost. These packages are designed to meet a moisture sensitivity level (MSL) of 3 for reflow temperatures of +260C; their tight mechanical tolerances make them ideal for automatic PCB reflow processes. The packages are RoHS compliant and will withstand lead-free solid reflow temperatures. In addition, the plating on the soldering surfaces is tin and does not present a risk of solder embrittlement caused by gold intermetallics. The design and materials have been engineered to ensure reliability and to allow devices to operate at +225C junction temperatures. Typical qualification tests include temperature cycle, high humidity operating life, high humidity, high temperature reverse bias, and high temperature gate bias.
Pulsed load-pull measurements were performed to evaluate the RFIC's power and efficiency performance. A load-pull system with passive tuners from Maury Microwave (www.maurymw.com) was used for the measurements. The pulse width was set to 9 s with a 10-percent duty cycle2 to study dynamic performance with minimal heating effects, and results for the MW7IC3825N/NB RFIC were found to be satisfactory for the full 3.3-to- 3.8-GHz band.3 Table 2 shows the load-pull performance for maximum efficiency, where efficiency refers to the drain efficiency of the two amplifier stages taken together. The device was found to deliver excellent flatness in terms of P1dB and drain efficiency performance from 3.3 to 3.8 GHz.
The LDMOS RFIC was found to provide two-stage drain efficiency of 40 percent. To anticipate performance results during the customer design phase, Motorola Electro Thermal (MET) and Root models for the MW7IC3825GN were derived and validated versus measured data, with both models incorporating die, package, and bond wires. The models were implemented in a design environment based on the Advanced Design System (ADS) from Agilent Technologies (www.agilent.com) and also validated under small- and largesignal conditions. Figure 5 shows load-pull simulations at 3.6 GHz. The dot contours are simulated P1dB contours, while the circled points are for measured P1dB optimum impedances. Figure 5 also uses solid contours to show simulated power-added efficiency (PAE) while star point are used for measured PAE optimum impedances.
Table 3 summarizes comparisons between modeled and measured data. The MET model achieved 0.5-ohm accuracy for its predictions of optimum impedances, Using measured load-pull impedance values as reference points, a demonstration board was developed for use in the 3.4-to- 3.6-GHz band. Printing most of the RF matching and fundamental decoupling networks minimized insertion losses of the matching networks while maximizing broadband response and repeatability. When the appropriate values of impedances were implemented, the board was tested under single-tone CW conditions. Biasing the device under the proper conditions to evaluate compression point, a gain better than 22.8 dB was obtained with flatness close to 0.5 dB from 3.4 to 3.6 GHz (Fig. 6). Performing power sweeps under these conditions verified that the output power at 1-dB compression was approximately 29 W, with two-stage efficiency close to 34 percent (Table 4). The device also shows excellent flatness in terms of gain, power, and efficiency across the operating bandwidth. When tuned as a drive, the device exhibits gain flatness of better than 0.5 dB.
With the device mounted on the same evaluation board, its response was characterized under WiMAX conditions. In a previous paper,3 it was tested with a 7-MHz WiMAX signal. For this study, a 10-MHz-bandwidth signal and 64QAM-3/4 modulation was used. The peak-to-average ratio (PAR) was 9.5 dB at 0.01-percent probability on a complementary cumulative distribution function (CCDF). The results of biasing the device for Class AB and fine-tuning the board are shown in Table 4.
When tuning was performed for final- stage (output) applications, and at +37-dBm average output power from 3.4 to 3.6 GHz, the two-stage efficiency was about 15 percent with an associated error vector magnitude (EVM) at -33 dB (the ETSI specification limit is -31 dB). The gain is about 25 dB across the band, and although the linearity performance is exceptional, added linearity can be obtained using digital predistortion (DPD) techiques. For instance, in Fig. 7, the evolution of relative constellation error (RCE) and efficiency is shown with and without DPD. An improvement of approximately 10 dB was obtained for RCE at +37 dBm output power, without degrading the performance of the other parameters, such as drain efficiency. Note that the use of DPD also enables the device to operate 3 dB higher in terms of power at -31 dB RCE.
The MW7IC3825N's flexibility allows a circuit designer to use it as an output power stage or as a linear device in driver applications. Simply by optimizing the bias point, and slightly modifying its PCB and using the same WiMAX signal as before, the performance shown in Fig. 8 was obtained. It shows that for +27 dBm output power, the ACP values are better than -52 dBc, while the EVM values are better than -36 dB (close to the linearity of the test signal generator). For 15 W average output power at a center frequency of 3.5 GHz, two-tone CW testing was performed to determine the third-order intermodulation distortion (IMD). The video bandwidth (VBW) resonance for this device is close to 50 MHz, which covers the potential 28 MHz carrier bandwidth that OFDM allows in WiMAX standards.
Finally, measurements were performed to characterize stability. The phase angles of a test load were varied to the equivalent of a 10.0:1 VSWR as might be found due to temperature variations from -30 to +85C, 20-dB output-power variations in dynamic range to P3dB, and DC voltage variations from +2 to +32 VDC. Under all of these extremes, spurious emissions remained below -70 dBc.
1. E. Lan et al., "High power density InGaP PHEMTs for 26 V operation," 2005 IEEE RFIC Symposium. Digest.
2. J. M. Coupat et al., "True pulse load-pull measurement setup for high-power transistor characterization," 2006 ARFTG Conference.
3. C. Cassan and P. Gola, "A 3.5 GHz 25 W Silicon LDMOS RFIC power amplifier for WiMAX applications," presented at the IEEE International Microwave Symposium (IMS), Honolulu, HI, June 3-5, 2007, 2007 International Microwave Symposium.