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Matching a technology to a new product design is not always easy, since each technology offers its own benefits under different conditions. For example, the debate between silicon-CMOS and gallium-arsenide (GaAs) semiconductor technologies was lively at the recent 2013 IEEE International Microwave Symposium (IMS) in Seattle, WA. Comparing the two technologies is not as simple as comparing the performance levels of their active devices.

The best way to compare device technologies is by analyzing them as part of a technology mix in a completed product. To choose between a CMOS or GaAs power amplifier (PA) module, for example, the surrounding required technologies—including passive devices, laminate, packaging, and surface-mount device (SMD) components required for each PA—should also be evaluated. Design software can speed and simplify such comparisons, under different conditions.

Product-level technology decisions are difficult because design tradeoffs must be considered as complexity is added to a base device technology. An informed comparison is possible by starting simply and rapidly adding complexity while evaluating corresponding technology tradeoffs. A methodical approach should be followed, where a proposed mix of technologies is evaluated by rapid virtual prototyping, starting at the device level and working through to the product level.

This way, the interactions between technologies can be evaluated within a proposed product. The results between two or more different technology combinations can then be compared at the top product level. This design methodology can be shown for GaAs- and CMOS-based technology mixes applied to PA module designs (Fig. 1).

Beyond CMOS Vs. GaAs: Picking The Right Technology, Fig. 1

With their high breakdown voltages and capabilities to handle high current densities, GaAs heterojunction bipolar transistors (HBT) are excellent active devices for RF/microwave PAs. To evaluate this design approach, the GaAs PA was based on the HBT process from WIN Semiconductors, which uses the Agilent HBT model from Agilent Technologies. Besides fitting the device characteristics well, this model has robust convergence, which is critical for large-signal co-optimization across different technologies. At the device level, the key design consideration is to mitigate reliability concerns. For a GaAs HBT PA, this means breaking the device into parallel fingers that are individually ballasted to prevent localized thermal runaway.

The design of a GaAs HBT PA will be based on a Class-E switch-mode configuration. One of the keys to this design is determining the required number of parallel active devices to achieve the target output power while also maintaining a long device operating lifetime. Since the circuit topology will drive the power and efficiency of this PA design, these needs should be evaluated at the circuit level. From the power requirements, it is possible to estimate the peak-to-peak and DC current levels to determine the number of device fingers. An electrothermal analysis can then be applied to verify the junction temperature.

The bias and power-control requirements for this GaAs HBT PA design should also be considered at the circuit level. In this case, the power-control function is contained in a separate integrated circuit (IC) based on a standard silicon CMOS process and simulated using equation-based symbolic devices. A common technique for controlling the output power of an active device is biasing the device under voltage-saturated conditions and controlling the supply voltage with a regulator; unfortunately, this approach suffers loss.

For this type of technology evaluation, it is important to pay attention at the losses at each step of the design. Degradations in performance can change a decision concerning a technology—one reason why the “rapidly added complexity” design methodology can help guide the choice of technology mix (Fig. 2).

Beyond CMOS Vs. GaAs: Picking The Right Technology, Fig. 2

Textbook Class-E matching networks incorporate a resonator that enhances the harmonic short circuit provided by the switching capacitor. A more practical realization is a standard inductive-capacitive (LC) impedance match that uses SMD capacitors and laminate inductors to transform 50 Ω at the antenna to the lower device-level impedance of about 2 Ω. This works well when the shunt Class-E capacitor is physically close to the low-impedance active device (Fig. 3).

Beyond CMOS Vs. GaAs: Picking The Right Technology, Fig. 3

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