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For the physical design of the GaAs PA’s matching networks, an inductor layout will be created on a four-layer laminate with a FR-4 dielectric core that can be used to generate an electromagnetic (EM) model for optimization. Using the model can help select the proper inductor values and circuit dimensions for this PA application (Fig. 4). The EM modeling process is repeated for each inductor, and then a fully integrated match is optimized. Complexity is added to this design by replacing the ideal capacitors of the model with discrete-valued capacitors from Murata Manufacturing Co. Ltd. A realizable circuit design results by performing the optimization with these discrete components.

Beyond CMOS Vs. GaAs: Picking The Right Technology, Fig. 4

Then, the plan for developing the GaAs PA involves simulating the output impedance match with the PA. The simulation analysis reveals that the device-level efficiency is not affected by the output match; however, some loss is apparent from the nonideal output match, causing a slight decrease in the power-added efficiency (PAE) and output power (Pout) of the PA, as was expected. Although expected, it is important to monitor such losses at every step in the design process.

The next step in the GaAs PA design involves integrating the laminate with the GaAs PA and mounting it into a 3.5 x 3.5 mm package. For a quick evaluation, the top metal layer of the GaAs die was modeled with the laminate substrate, using a three-dimensional (3D) electromagnetic (EM) simulation of the bond wires to analyze their inductances and mutual coupling. This provides a good estimate of potential performance degradations at the interface level, essential when evaluating a technology mix.

To add even more realistic complexity to this analysis, the PA’s backside ground via holes were connected to the laminate’s ground paddle. When this was first done, the amplifier’s PAE dropped by 9% and the output power dropped by approximately 1 dB. Fixing such losses can be quite difficult at the product level. But at the interface level, it is possible to extract the small-signal ground inductance of the combined via and die-paddle structure.

Next, to troubleshoot the problem, an ideal via is replaced with a lumped inductor at the circuit level. It is easy at this point to change the load and source impedances to find a more optimal combination. Finally, at the product level, the output impedance match is adjusted to regain optimum PAE and output power. This demonstrates the power of this design approach, with the flexibility to tune and optimize the amplifier circuitry while also modeling the interconnections.

The GaAs-based design approach includes accurate model values for SMD capacitors, the circuit laminate, and the interconnections. To evaluate the viability of this technology mix and understand its tradeoffs, simulations are performed at the system level, with modulated sources to accurately model the signals in actual systems. Using the laminate with SMD components provides numerous advantages, including being simple, flexible, and providing an output match that is tunable and with high quality factor (Q). The disadvantages include the limited opportunities for size reduction with SMD components, a bias topology that degrades the amplifier’s PAE, and only limited use of the lower laminate layers.

For the PA using a CMOS-based technology mix, the power-control function will be integrated on the IC. The matching transformer could be integrated on the same IC but, for this design example, an integrated passive device (IPD) transformer will be used to better illustrate how to evaluate a less-conventional technology approach.

Active RF/microwave devices for PAs are typically large and must handle relatively high voltages, which is a challenge for devices with smaller CMOS gate lengths. Since transistor operation is based on a MOS capacitor in the CMOS-based mix, the dominant reliability mechanisms are related to breakdown voltages. The RF swing across the junctions is limited to 2x the device operating voltage, presenting a challenge to achieve RF output power above 1 W. Several approaches must be taken to mitigate this reliability challenge, approaches which span from the circuit to the interface levels, with tradeoffs existing among output power, circuit size, and reliability.

At the circuit level, a Class-E configuration works well because switching-mode operation mitigates reliability concerns across the gate-drain junction while a differential cascode topology divides the RF voltage-swing between several devices. Power control is performed in a closed-loop fashion by sensing the RF signal at the output and adjusting the bias voltage on the top cascode device.

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