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An initial load-pull analysis of a standard differential cascode topology reveals that the RF voltage swing is not well balanced between the upper and lower devices, with the upper device encountering a higher voltage swing. Using 2Vd as the reliability limit, a circular area on a Smith chart will show the region of unreliable operation which is, unfortunately, the entire usable range of the PA (Fig. 5). This is due to the load impedance presented to the bottom device, which is close to a short circuit since the cascode’s gate node is a virtual ground.

Beyond CMOS Vs. GaAs: Picking The Right Technology, Fig. 5

A more practical topology for the CMOS technology approach is one that allows for independent control of the cascode gate impedance. To achieve this, the gate feeds for the cascode device are broken up and separately terminated with a shunt capacitor. Once this is done, the voltages can be more evenly balanced across the devices, and the unreliable range of operation shifts outside the usable range of the PA.

A good approach for improving reliability at the interface level is to use a transformer to combine, in parallel, several stacks of devices into a single load. This allows each stack to see less of a voltage swing. For the CMOS technology mix, a discrete transformer designed on a 10-μm-thick metal IPD process from ON Semiconductor was considered as a candidate.

Each primary turn is a different color that weaves from outer to inner turn, driven differentially. The secondary turn is one long series inductive coil to ground (Fig. 6). As with the GaAs technology mix, the transformer for the CMOS-mix PA was parameterized to create an optimizable EM model. Simulation of the load impedance presented by the transformer revealed that a pre-match inductor was needed for each of the transformer’s primary taps to provide the desired load impedance for the CMOS PA.

Beyond CMOS Vs. GaAs: Picking The Right Technology, Fig. 6

The CMOS PA circuitry now includes four power cells and the IPD transformer, and this was driven differentially at the input using a balun and matching inductor. This combination yields drain efficiency that is close to the load-pull result, but with a drop in amplifier PAE due to the IPD pre-match inductor.

To house this PA circuitry, a standard 4 x 4 mm QFN package from Amkor was selected, with the addition of three-dimensional (3D) bond wires to model the mutual inductance and provide a means for optimization. Since the structures are differential, adding the mutual coupling of the bond wires shifted the results. Once again, the “rapidly added complexity” methodology was applied to understand and address the problem. In this case, the bond wire height and proximity were adjusted to minimize the coupling (Fig. 7).

Beyond CMOS Vs. GaAs: Picking The Right Technology, Fig. 7

For the CMOS-based PA design, along with optimizing Pout and PAE, it will be necessary to consider the voltage swing across the devices’ worst-case high Vbatt battery-voltage conditions for reliability reasons. The voltage swings that were achieved in the CMOS design are barely acceptable; additional steps should be taken to mitigate that voltage swing by clamping or regulating the control voltage. To evaluate the CMOS technology mix at the package level, the inductors and transformer were chosen as separate and optimizable.

The PA based on the CMOS technology mix is very different compared to the GaAs-based design. It offers numerous advantages, being simple and compact, with integrated power control and all matching realized on the IPD. But it also has disadvantages, with the discrete transformer limiting the number of stacked active devices in the cascode, limited impedance tunability with the transformer, and with PAE somewhat degraded by the use of the pre-match inductor.

By completing two functioning designs, it is possible to realistically compare the two technology mixes and how they might serve different applications. The insights gained at this level are far more meaningful and invaluable than a simple device-level comparison of technologies. This methodology makes it possible to compare two different technology mixes in weeks or even days, eliminating the risk associated with choosing a poor technology mix. The capability to move up and down levels while rapidly adding complexity with an iterative design approach provides a great deal of insight into how the different technology mixes will perform in the final product designs.

It should be noted that to implement this design methodology, the following are required: access to different technologies and PDKs, integrated EM simulation technology, parameterizable and optimizable physical layout for circuits, and the capability to analyze performance with modulated signals. The use of this “rapidly added complexity” methodology is broadly applicable and can help reduce risk early in the design process, as well as eliminate problems and speed time to market.

Editor’s Note: Readers seeking additional information on this GaAs versus CMOS technology comparison, including Advanced Design System (ADS) model files for both CMOS and GaAs PA module designs, are invited to visit Agilent Technologies’ page on the topic.

Matthew Ozalas, RF Power Amplifier Designer

Agilent Technologies, Agilent EEsof, 5301 Stevens Creek Blvd., Santa Clara, CA 95051; 408-345-8886, FAX: (408) 345-8474.

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