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Accurate models of surface-mount-technology (SMT) components are often required when using modern high-frequency computer-aided-engineering (CAE) circuit simulators. This is becoming more commonplace as the frequency range and use of available high-frequency SMT components increases. Accurate models mean fewer design iterations, less troubleshooting, and shorter time to market for a design. Fortunately, such models can be derived from S-parameter measurements—but those S-parameter measurements must be sufficiently reliable to ensure model accuracy.

Obtaining reliable S-parameters of an SMT component is not a straightforward process because the component needs to be mounted on a test jig. Therefore, the combined response of the SMT component and the test jig is measured by the measurement system and the electrical contributions of the test jig must subsequently be removed. The process becomes more difficult as the frequency of the SMT component rises.

There are several ways of measuring the S-parameters of an SMT component using a vector network analyzer (VNA).1,2 These include port extension, de-embedding, and calibration on a printed circuit board (PCB). Other approaches, such as thru-reflect-line (TRL) techniques, can work well but are difficult to use with wide (decade or greater) bandwidths, particularly when extended to lower frequencies.

Port extension is the simplest approach. With this technique, coaxial cables are connected to the VNA and a calibration is performed by attaching coaxial calibration standards to the ends of the cables. The measurement reference planes are then established at the ends of the cables. Then, the test jig containing the SMT component is connected to the cables and the measurement reference planes are extended (using the VNA’s electrical delay capability) to the mounting pads of the SMT device.

The disadvantage of this approach is that effects due to impedance mismatches (for example, from coaxial-to-microstrip connectors on the test jig) are not removed from the measurements. In addition, losses associated with the microstrip lines on the test jig that connects to the SMT component are difficult to remove from the measurements.

De-embedding methods require that each half of the test jig is characterized separately. This is usually achieved by using a VNA to measure each half of the test jig as a two‑port network. The SMT component is then inserted between the two halves of the test jig and the combination of test jig and SMT component is measured using the VNA. The test jig information (i.e., the S-parameters of each half of the test jig) is then used to mathematically remove (de-embed) the effects of the test jig from the overall measurement of the combined test jig and SMT component.3

This approach can yield very good results. However, it is usually not straightforward to obtain accurate two-port S-parameter measurements of the test gig. This is because each half of the test jig effectively behaves like a non-insertable two-port network. This calls for a non-insertable VNA calibration to be performed involving, for example, a combination of both coaxial and planar (i.e. on-PCB) one-port standards and a non-insertable two-port thru connection (for example, using the “unknown-thru” calibration technique.4,5

VNA system architecture

Calibration on PCB relies on calibration standards that are fabricated directly on the PCB test jig. For example, this technique can be realized using a conventional short-open-load-thru (SOLT) calibration strategy. The approach requires a more complicated test jig, but has the advantage that—provided that the calibration standards are of good quality and their characteristics are precisely known—test jig effects are automatically removed during the calibration process. It therefore avoids the disadvantages of the first two techniques (the problems of mismatch and loss with the port extension method, and the problems of performing calibrations in non-insertable environments with the de-embedding method).

A cost-effective implementation of the calibration-on-PCB method of obtaining computer models for SMT components using S-parameters to 6 GHz has been developed using a test jig based on FR-4 PCB material. In addition, the instrumentation employs a PC-driven VNA, an 8-GHz model LA19-13-036 from LA Techniques (Surrey, UK) to help lower costs. Results will be presented for a typical SMT component using this low-cost solution, with the VNA accuracy verified against the UK’s primary national standard S-parameter measurement facility.

FR-4 test jig

The VNA offers a cost-effective alternative to more traditional desktop VNAs. By transferring most of the signal processing and display requirements to a PC or laptop computer, the overall cost of the hardware is significantly reduced. In addition, the instrument uses a novel VNA architecture (Fig. 1) with only two receivers—rather than the customary three or four receivers—without significant loss of performance compared to full-sized (and full-priced) commercial VNA systems. The PC-based VNA achieves a dynamic range to 120 dB across a frequency range of 300 kHz to 8 GHz. It tunes with 10-Hz frequency resolution with sweep speeds to 200 μs/point. This level of performance is suitable for implementing the intended application of a cost-effective calibration-on-PCB test method for measuring SMT components to 6 GHz.

The SMT component chosen to illustrate the implementation of the calibration-on-PCB method is a model LFCN-2500 filter from Mini-Circuits.7 This is a DC-to-2.5-GHz ceramic lowpass filter housed in an FV1206-type package. It has a 3-dB point around 3 GHz and stopband attenuation of approximately 40 dB at 4 GHz.

Figure 2 shows a photograph of the test jig used for the lowpass SMT filter. Apart from the SMT component to be tested, the test jig also contains all the standards needed to perform an SOLT calibration of the VNA. These are a short circuit, open circuit, near-matched load, and thru-line standard. The offset lengths of these standards are designed to achieve measurement reference planes, after calibration, which are located directly at the position of the input and output of the SMT component. Although the test jig was designed for the LFCN-2500 filter, the same approach can be used to design test jigs for other types of components.

PCB stack-up construction

Figure 3 shows the PCB stack-up construction for the test jig. The PCB uses four layers and has an overall finished thickness of 1.6 mm. This arrangement results in a physically rugged test jig that is able to accommodate the most widely available types of edge-launch SMA connectors.8 The width-to-height (W/h) ratio of the signal line is chosen to be 1.763, which results in a microstrip line with characteristic impedance of 50 Ω. The track width is 0.67 mm, consistent with the size of the SMT component to be tested. (The relative permittivity of the FR-4 PCB material, εr, is assumed to be 4.6.)

Apart from the microstrip lines [technically, these are grounded coplanar-waveguide (CPW) transmission lines, but the gap is large enough to make the microstrip mode dominant] on the top layer, all four layers of the test jig are grounded copper—the grounding being achieved using closely spaced interconnecting viaholes (Fig. 2). This means that only the top dielectric layer determines the impedance of the microstrip line; this, in turn, allows the 50-Ω line width to be narrow, consistent with the size of the SMT component to be tested.

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