The channel bandwidth of a TD-LTE system is 20 MHz. The corresponding sample clock for DACs and ADCs in the system is 30.72 MHz, according to the specification of the LTE physical layer.6 The sample clock is supplemented by a clock synthesizer which integrates a phase-lock-loop (PLL) circuit and the clock-distribution circuit. The PLL function of the clock synthesizer generates a low-jitter 30.72-MHz clock signal from the reference clock, while the clock-distribution circuit provides a multiple output to the converters in the baseband circuit board. All reference signals on the baseband boards, as well as RF transceiver boards, are buffered from a Global-Positioning-System (GPS) clock by a clock buffer chip on the back board.
| Download this article in .PDF format |
This file type includes high resolution graphics and schematics when applicable.
In a DAC-based system, digital interpolation can be used to relax the requirements on the output anti-image filter. The interpolation process does not increase the amount of information contained in the original input data stream; instead, it adds extra data points, increases the output data rate, and makes it easier to filter the images. The on-board AD9779A DAC from Analog Devices contains an integral interpolator which doubles, quadruples, or octuples the input data rate by stuffing zeros between successive samples and then filtering the result.
Figure 4 offers a comparison of a 10-MHz sinewave signal with interpolation factor set to 8 and the same signal without interpolation. For a DAC without interpolation, images are located at:
NFDAC ± Fout
and follow a sin(x)/x envelope [Fig. 4(a)]. With an 8x interpolator, these images were effectively suppressed at lower frequencies [Fig. 4(b)]. To remove undesired images and spurious signals far from the carrier after interpolation, only a very simple post-DAC analog filter is needed.
A superheterodyne topology similar to that presented in ref. 7 was adopted for the best performance. The transceiver can support eight frequency channels in 20-MHz steps from 3.411 to 3.551 GHz. Different frequency bands can be set by configuring the PLL on the circuit board in accordance with the decoded commands sent from the main processor. Figure 5 shows the architecture of the RF transceiver while ref. 8 offers design consideration and more detailed measurement results for some key figures of merit, including output power, linearity, error vector magnitude (EVM), and third-order intermodulation distortion (IMD3).
Differential I/Q analog signals between RF transceiver and baseband board are interconnected through the high-speed connectors installed in a backboard. Besides I/Q signals, the interface also links the transmitting power control signal, the receiving gain control signal, the transceiver switch signal as well as the configuration signal forfrequency synthesizers.
Figure 6(a) shows the designed subsystem, in a configuration which offers some flexibility in terms of the number of channels. The first two boards from the left are power-supply boards providing DC-DC conversion from -48 to +6 VDC and -48 to +3.3 VDC to produce the voltages required by the baseband boards and RF circuit boards, respectively. The first circuit board from the right is the controller board, which handles all control signals to the RF and baseband interface. The middle section is for baseband and RF boards. One baseband circuit board, together with two RF circuit boards distributed on both sides, consists of a 2x2 MIMO unit. With the top configuration,the subsystem consists of four 2x2 MIMO units, which supports an 8x8 MIMO channel. Figure 6(b) shows the separate baseband and RF circuit boards.
In this MIMO system, EVM, a modulation quality metric widely used in digital communication systems, is thoroughly optimized to achieve excellent performance. Using the 89600 vector signal analyzer (VSA) software from Agilent Technologies, impairments to EVM such as magnitude error, phase error, frequency error, and in-phase/quadrature (I/Q) offset can be analyzed to troubleshoot potential problems in the design.
In the first test case, various transmitter specifications, such as EVM, signal-to-noise ratio (SNR), and adjacent channel power ratio (ACPR) were measured. For testing, complex baseband I/Q signals with QPSK, 16QAM, and 64QAM modulation types was created in MATLAB® software from MathWorks. The signals were downloaded to the FPGA on the baseband board and then fed to the RF board for modulation and upconversion to generate the required higher frequencies. The baseband I/Q data symbol rate was 15.36 MSamples/s, with a bandwidth of 19.2 MHz that considers the root-raised cosine filter having an alpha value of 0.25. The average output power of the power amplifier on the RF board was +23.1 dBm. For this testing, measurement results are listed in Table 1, with a VSA-produced constellation diagram shown in Fig. 7.
In the second test case, the receiver’s EVM and SNR were measured with QPSK, 16QAM, and 64QAM modulation. The parameters of the reference signal were same as in the first case. Complex baseband signals were modulated to 3.415 GHz internally within a model E4438C vector signal generator (VSG) from Agilent Technologies. Figure 8 shows the measured results, with an input dynamic range of -70 to -10 dBm.