Global Positioning System (GPS) receivers are poised to play a critical role in wireless communications as a result of the United States Federal Communications Commission's (FCC's) E911 directive and location based services (LBS) expected to follow on the heels of the mandate. Successful E911/LBS products and services will require solutions with features that can implement GPS in mobile telephones, for low cost, with low power consumption high accuracy, high sensitivity, and good noise immunity.1

A GPS receiver typically comprises two functions: the radio front end and the baseband digital signal processor (DSP). Complementary-metal-oxide-semiconductor (CMOS) digital technology improvements now allow baseband designs to be ported across silicon vendors and be realized at the system level using reliable processors such as the DSP cores from CEVA (Northampton, England). Ideally, the RF front end would also be available in a standard process and portable across a variety of suppliers.

Support of embedded GPS solutions involves the development of an approach to provide appropriately featured silicon GPS on RF integrated circuit (RF IC) solutions with minimal redesign time. What follows is an explanation of that approach and how software modeling methods were used to evaluate RF IC design compromises, based on the Advanced Design System (ADS) simulator from Agilent Technologies (Santa Rosa, CA).

Radio-receiver design normally breaks down into two aspects: the top or system-level requirements, such as chip gain and frequency planning, and the individual circuit block performance. Traditional design approaches use separate tools for system, DSP, and RF design. RF IC designers typically must reconcile different modelling results of analog, digital, and RF signals in high-density circuits. For example, integrating bipolar transistors alongside passive components and high-speed CMOS logic introduces significant uncertainty in the operational behavior of the circuits, illustrated by the need to model a phase-locked loop (PLL), where the designer is faced with having to co-simulate digital counters/dividers with the analog voltage-controlled oscillator (VCO).

The initial design and development of a GPS radio requires a careful design process focused on the particular and specific attributes of the target process technology. Converting this into intellectual property (IP) for porting to other processes requires an approach that will reduce the development time and cost significantly below that of the original design phase. Indeed, most customers have very short development times that can be typically 50 to 70 percent of the time taken for the first demonstrator design.

As a result, a methodology was needed that would support frequency-domain and mixed-domain simulation technologies; optimization and statistical design tools; and additional device, system, and behavioral models. This methodology would allow both a top down and bottom up approach so that transistor level changes due to the different process models can be transported to the system level. ADS allows the use of both time-domain and harmonic-balance nonlinear simulation techniques.

This approach made it possible to compare the trade-offs of a single-chip GPS receiver on an advanced 0.13-µm CMOS process and a design developed with separate RF and digital chips (allowing the digital IP to be incorporated into a host chip). The software helped determine that overall system performance would benefit from a separate radio on an advanced silicon-germanium (SiGe) BiCMOS process (Fig. 1) The radio design is the XPERT-GPS RF platform (Fig. 2) which provides the radio front end for a GPS developed for use in mobile communications, such as handsets and personal digital assistants (PDAs).

The radio design uses a SiGe bipolar CMOS (SiGe BiCMOS) process to achieve a high level of integration, a noise figure of less than 1.5 dB, low power consumption, and low system implementation cost. The radio downconverts the GPS L1 band at 1575.42 MHz and performs a selectable 1-b sign/magnitude or 2-b-sign/1-b magnitude analog-to-digital (ADC) conversion to produce a baseband signal at 3.78 MHz, which feeds the baseband processor.

A variable frequency plan provides the necessary local oscillator (LO) and baseband clock frequencies using an external temperature-compensated crystal oscillator (TCXO), enabling the use of a single board design for different reference clocks from 10 to 26 MHz. Alternatively, a single crystal may be connected to the device using the built-in oscillator circuitry for applications requiring a lower-cost solution.

Key challenges on the RF subsystem are to achieve the GPS requirements of image rejection simultaneously with the capability for co-operational functionality within a mobile-telephone handset. Coprocessing functionality must address both the hostile RF environment and the need to optimize the scarce resources of space, bandwidth, DC power, processing power, or millions of instructions per second (MIPS in terms of clock cycles) in the presence of interferers generated by the mobile-telephone protocols.

GPS RF models were developed at multiple abstraction levels using ADS to generate and send GPS signals through to a single-channel baseband correlator for demodulation. With this approach, it was possible to define, optimize, and specify the performance of each block for silicon implementation, simplifying the task of porting the design to another semiconductor process. The approach also allows the RF IC IP to be used as a CEVA block in a customer's test bench, thereby reducing the time taken to simulate and derive probable performance in a given system environment.

Figure 3 shows the top-level schematic of the RF IC in the design simulator window. The simulator allows the properties of each block to be displayed so that simulation environment parameters can be easily observed. This is important since each symbol may contain subhierarchy information.

The simulator must be able to model key system performance parameters, including noise, linearity, gain, sensitivity, frequency, and modulation. The power spectral density (PSD) for a typical GPS spectrum is shown in Fig. 4 along with thermal noise. Note the sinx/x nature of the GPS signal. The RF IC must process a signal that is about 20 dB below the noise level; only by performing integration until the signal-to-noise ratio (SNR) is greater than zero can the receiver recover the GPS signal from the noise.

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The simulator's many functions support a large variety of test scenarios. The harmonic-balance simulator, for example is used mainly for evaluating RF block specifications for nonlinear behavior where signals mix or compress in the frequency domain (as in mixer noise analysis). The complete system is then cosimulated using Agilent Ptolemy, an ADS module. Together with the circuit envelope simulator, it allows the front end of the code recovery and correlation digital logic in the baseband to be cosimulated with analog blocks so that effects on data demodulation can be observed. This is an efficient technique where the time step is chosen from the modulation bandwidth rather than the highest frequency of the system. The technique is very efficient when analyzing modulated waveforms since calculations are only done around the frequency of interest. For example, a time-domain analysis with SPICE might use a time step of say 50 ps when simulating a mixer with 1.6-GHz LO and therefore result in long simulation times if the frequency band of interest is three times the frequency of the LO.

A GPS receiver's capability to operate in the presence of unwanted frequencies is a good indicator of the design's suitability for use as an embedded receiver within a cellular telephone. The telephone's own frequencies can act as potential jammers for the GPS receiver depending on their power levels (Table 1).

Blocking/jamming immunity is a measure of the receiver's capability to capture GPS signals in the presence of interfering signals. This refers to the receiver capability to reject unwanted images that appear within the same frequency spectrum as the desired image, fif. For example, an unwanted image is generated by any spectral components at frf + 2fif mixing with flo.

Figure 5 shows the nonlinearity of the GPS RF IC as a function of the jamming frequency. The receiver remains linear with GPS signal levels of −130 dBm and jammer power levels to about −90 dBm. The incorporation of GPS in a cellular handset means that a jammer will be operating nearby at the cellular frequency, about 1800 MHz in GSM systems.

A high jamming power level can cause the generation of spurious signals if the level exceeds the linear range of the GPS receiver's various circuit blocks. Out-of-band jammers can mix with spectral components to create unwanted mixing products (spurious signals) in the same frequency band as the desired signal, fif. If the power levels are high enough, the resulting spurious products may exceed the linear range of the circuit, resulting in the circuitry's inability to retain GPS signal lock. For the jamming scenario, an output level of +33 dBm was used to simulate the incident jamming power level transmitted by the GSM antenna. A front-end filter model was used in the simulation.

For higher-level GPS system simulations, the Agilent Ptolemy and circuit envelope cosimulation environment allows analysis of demodulated data at baseband. It also allows operators to view the modeled RF IC cosimulation test bench (not shown) that was used to define the system performance in schematic form. The schematic diagrams were used as the basis of harmonic balance and circuit envelope simulation environments. Such test setups even allow parameter sweeps (such as interferer power levels) with the capability of observing the effects on the carrier-to-noise ratio (CNR). Depending upon the circumstances, a CNR of about 40 dB/Hz or more would be expected for good GPS performance.

Figure 6 shows cosimulation results on the RF IC with input thermal noise, phase noise, and receiver noise figure. The estimated CNR in the data demodulator is shown as a function of time; the length of the modulated code is 20 ms. The spectrum also shows the correct shape for a band-limited IF signal.

Figure 7 shows an I/Q polar plot of the demodulated GPS signal. In this case, the GPS signal carries no data and, therefore, only one symbol is shown. This is a better way of looking at the quality of the demodulated signal; a poor signal to noise ratio will result in a greater distribution of the symbols. As noise and phase contributions are removed, the CNR increases and symbol distribution becomes tighter as the SNR improves.

A key consideration in designing a GPS RF IC involves the IF filter: it must provide adequate rejection of out-of-band jamming signals but not occupy too much of the semiconductor die area or consume too much current. Figure 8 helps evaluate these trade-offs, showing a simulation that evaluates CNR degradation as a function of filter bandwidth and order. It indicates that the CNR has an inverted bathtub response with the bandwidth of the IF filter. Recalling the sinx/x response of the GPS signal, bandwidths narrower than about 1.5 MHz cut-out part of the fundamental as well as the lobes of the sinx/x waveform, effectively reducing the SNR. For bandwidths above approximately 3 MHz, the increase in SNR contained in the sidelobes is outweighed by the increased integrated noise, resulting in degraded CNR. In terms of filter order, there appears to be little gained by using filters of more than four or five order, since there is no further increase in CNR. This type of analysis leads to the use of a filter that provides adequate CNR performance without added complexity and cost.

The ultimate measure of a GPS receiver's performance is the design's capability of tracking GPS satellites. Figure 9 shows the receiver's early-prompt-late correlation outputs using the XPERT-GPS RF in the NS3000 GPS platform measured over an integration time of 16 ms. The baseband produces early, late, and prompt versions of the code; the resulting correlation triangle provides a visual guide to the quality of the GPS signal through the XPERT-GPS RF. The three distinct steps can clearly been seen.

To verify the simulated results, characterization of the RF and IF sections were carried out separately. The RF strip, consisting of an LNA, a pair of I/Q mixers, and a combiner with drivers, was evaluated as a single block with an input signal at 1.575 GHz and output at the first IF. Key performance parameters are summarized in Table 2, with a complete module of the GPS receiver used to obtain some of the system measurements shown in Fig. 10.

The authors have found ADS to be a powerful tool in the analysis and design of the XPERT-GPS RF, helping to define and verify the next generation GPS radio at a number of levels, from block-level simulation through system simulations, including code recovery/correlation at baseband. ADS has made it possible to identify and explore the key parameter trade-offs in GPS receiver design.

In addition to a better design process, this development methodology renders design techniques and trade-offs more visible to designers and IP users. Design engineers, product developers, and system integrators are able to verify the suitability of designs and IP for their needs, reducing risks and costs while improving time to market. The chip is commercially available as the MAX2741 from Maxim Integrated Products (Sunnyvale, CA).

REFERENCES

  1. P. Anderson , J. Bickerstaff, "GPS for the E911 Location Requirement − The Practical Approach," ION 2001.
  2. Elliott D. Kaplan "Understanding GPS: Principles and Applications."