Meld Load-Pull Tests With EDA Tools

(Swept input-image impedance, source-pull, may be implemented, but is not considered here. Harmonic terminations are not presently supported in this system. Both input-image impedance and harmonic terminations have secondary effects on their PMs.) Complex load, Γ, can be decomposed into two scalars yielding six independent variables that must be swept in a methodical fashion. Commercial systems normally sweep the load reflection coefficient, Γ, in polar coordinates. This sweep is usually in the form of:

where:

Γ_load = the reflection coefficient presented to the device under test (DUT),

Γ_offset = a constant complex number,

|Γ_s| = the swept magnitude, and

Θ_s = the swept angle.

Graphically, this expression is a series of concentric circles with a fixed offset from the center of the Smith Chart. Over a narrow band, this specification may be adequate. However, over a wide band the Γ_offset should change over frequency to keep the load at or near the peak performance region requiring that Γ_offset be swept also. Since the Γ_load specification method is not very insightful and the addition of a third swept variable is complicating, a new, more intuitive method of specifying the load is needed.

Small-signal S-parameter measurements may be used to construct an equivalent circuit for the output of a power device. Converting the S-parameters to an equivalent parallel network reveals that the output load behaves as an admittance with fairly static values for conductance and capacitance (an unmatched device operating below resonance). This model makes intuitive sense from a physical perspective. The real part of the admittance represents FET resistance R_ds while multiple drain (collector) cells formulate a shunt capacitance. An unmatched LDMOS device, for example, appears to be well represented by a parallel R_p and C_p model. Equation 3 shows the admittance formula for a parallel R_pC_p network while Fig. 1 shows this trivial circuit:

SEE EQ. 3

Instead of sweeping of Γ, a more effective approach may involve sweeping the constituent admittance components (R_p and C_p) presented at the device lead plane. The next step is to determine how to establish these sweep values.

PA output networks are generally not conjugate-matched systems for the real part of the load. Typically, the desired power output and available supply voltage determine the real part of the load presented to the device, not the device impedance. Equation 4 shows the classical approximation for the real part of the load:

SEE EQ. 4

where:

V_dd = the supply voltage,

V_sat = the device saturation voltage, and

P_out = the peak output power.

RF power designers will recognize this equation as an estimate of the required parallel resistive load to achieve output power for a given supply voltage, V_dd. This equation is insightful because of its familiarity and the way it links the real part of the load to actual measurement system terminal parameters. Therefore, the real part of the load will be swept about R_p as defined by Eq. 4.

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Conjugate matching is used to define the imaginary part of the load. As Fig. 1 shows, a capacitive susceptance is seen looking into the device. Therefore, to achieve a conjugate match, a negative capacitance, C_p, is the desired swept parameter. This admittance formulation intrinsically provides frequency compensation through the Ω scalar. Load-pull measurements are center tuned over a much wider frequency range than when using the frequency-independent γ formulation. The R_pC_p sweep produces meaningful data points, not the far out of bound points produced by the Γ at some states. This minimizes useless data and speeds up the measurement process. Additionally, this load viewpoint is comprised of familiar circuit elements that are easy to understand in physical significance. As a result, Eq. 1 can be rewritten as:

SEE EQ. 5

This is the sweep and order method used in the Motorola load-pull system. This is also the equation that will be linked to the EDA tools described later. (This load formulation can be generalized for nonconstant R_p and C_p in the case of an internally matched device or where package parasitic elements are influential.). Figure 2 compares the Γ and admittance sweep differences on the Smith Chart. Parameter R_pC_p is swept across the constant conductance circles in sectors on the chart. The center of the cluster naturally shifts as frequency changes.

Figure 3 shows a generic block diagram of the measurement system. It consists of directional couplers, input/output (I/O) electromechanical tuners, test equipment, and a computer controller with GPIB bus. The fixture-device under test (DUT) includes the transistor and input and output fixture circuits. Typically, these fixture circuits perform a section of prematching since the device I/O impedances are extremely low.

Measurements are referenced at the device lead plane including the performance and the swept independent variables. To accomplish this, circuitry leading to/from the device lead plane to the respective directional coupler is carefully characterized prior to load-pull measurements. Two-port tuner S-parameters are read and interpolated at each load state. The fully characterized system permits de-embedded measurements at the device lead plane. Power-in is also referenced at the lead plane. At each test state in the six dimensional sweep, the input tuner is set to achieve a conjugate match (or as desired if applying source-pull) at the input-tuner-fixture/DUT plane. Device input impedance is then calculated since a calibrated vector network analyzer (VNA) is part of the test equipment. With the knowledge of the device input impedance, system input losses are calculated and the drive signal is compensated to overcome tuner and matching losses. Thus, the drive power independent variable is referenced at the device plane and independent of the dynamic circuit losses (which can be substantial for low impedance devices). De-embedding is also required on the output side to set the tuner. The R_pC_p load is referenced at the device plane and therefore the output tuner Γ is calculated to provide these known loads back at the device plane. Eliminating all fixture dependencies is critical when the goal is to capture device performance only.

The measurement system is capable of reading power-out, current drain, linearity, and input impedance. Efficiency can be calculated from these measurements and the independent variables. The test-signal source (a dual arbitrary signal generator) can produce CW, two-tone, or complex modulation waveforms. A vector signal analyzer can assess linearity in terms of intermodulation distortion (IMD) or adjacent-channel coupled power ratio (ACCPR). Once a load-pull measurement is completed over the six independent variables, test data are stored in a database where they can be extracted by multiple analysis software such as visualization tools or circuit simulators.

Hewlett-Packard Co. (now Agilent Technologies) developed the CITIfile (Common Instrumentation Transfer and Interchange) format for computer/instrumentation data exchange and subsequently adopted it to the MDS and ADS EDA tools. CITIfile is suited for load-pull data since it can support an arbitrary number of dependent and independent variables. One requirement is that the independent variables must be methodically swept—that is, the same inner values of the sweep must be identical. In the measurement system presented here, the order of the independent variables is frequency, R_p, C_p, supply voltage, bias current, and drive-power. Thus, for each frequency, the five independent variables below it must take on the same values to be CITIfile compliant. (The frequency tracking benefit of the R_pC_p load descriptor becomes clear.) Before the development of the present measurement system, load-pull CITIfiles were built by curve-fitting measurements. Curve-fitting added an additional step, which became very difficult to implement with additional independent variables. The customized measurement system is compatible with CITIfile by system design, and therefore no intermediate mathematical manipulation is required. The measurement system automatically places the load-pull data in a tool independent database. When a designer requires access to the load-pull data for the circuit simulation, a custom Labview utility is executed allowing perusal of the database. The utility allows the user to select the pertinent operating space and constructs a CITIfile about those terminal conditions. Next, the CITIfile must be linked to the EDA environment.

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Agilent EDA tools support the concept of a DATASET object. This object holds either simulation information or data imported from the outside (such as the case here). The DATASET has the ability to read a CITIfile through appropriate menu selections in the respective tool. Once a CITIfile has been read into the DATASET, load-pull data is linked into the EDA environment and measurements may be viewed by ADS data display. However, one more step is required to link the data to the simulator. In the schematic environment, a special component called the DataAccessComponet (DAC) must be instantiated on the schematic to permit the simulator to process the data. The DAC (or DATASETVARIABLE in MDS) points to the file containing the measured data, makes the dependent and independent variables accessible to the simulator, and can support up to ten independent variables. In essence, the DAC implements Eq. 5 in the simulation. The DAC is more than just a lookup table; it has the ability to interpolate between independent variables. Interpolation enables optimizations providing continuity to the dependent data. Details on optimization will be covered later.

ADS has the capability to graphically display load-pull data directly from the measurement system without passing through the simulator. Many different graphical cross-sections can be displayed since Eq. 5 is a six-dimensional relationship. Several data display graphics will be presented as examples of analyzing the measurements. The examples shown here are based on a Motorola MRF9045M LDMOS device operating at its rated 45-W output-power level in the 700-to-1000-MHz range.

Power out and efficiency versus load are shown in Figs. 4a and 4b. Performance variations are plotted against two independent variables represented by the equivalent parallel R_pC_p presented to the device output. The capacitance sweep (C_p) is shown on the x-axis while the multiple traces show variations in parallel resistance (R_p). Essentially, the plots depict Eq. 5 with R_p and C_p set as the swept ordinates (wildcards) and the other four variables fixed. Figure 4 shows, for example, that the peak power occurs at approximately 45 pF and 8.5 Ω. Efficiency peaks at a slightly larger capacitance, approximately 50 pF. If other frequencies were plotted in this format, it would be seen that the peaks remain relatively constant at these capacitance values for the respective parameters, lending credibility to the R_pC_p sweep method. Linearity and gain can be plotted similarly while complex device input Γ can be displayed on the Smith Chart. Concurrently generating these plots enables viewing all pertinent performance metrics versus load. Plots versus the other independent variables can also be displayed by fixing the load wildcards and enabling the sweep of other terminal variables. For example, drive-up performance or frequency dependencies can easily be viewed by making them the wildcard variable in the graph. A further enhancement is to add "slider controls" to the other variables to vary the values in those dimensions. Figure 5 shows that contours can be displayed using the ADS built-in polar contour function. Figure 6 illustrates a three-dimensional (3D) power-out versus load plot where the data have been imported into a mathematical analysis package (the HiQ™ package from National Instruments). Visualization may be accomplished by sweeping a third independent variable (such as power-in) to create an animation. Clearly, the simulation tool and other mathematical packages enable the designer to present and analyze the raw measured data equivalent or superior to the commercial measurement systems. Data presentation, however, is just an initial step in using the measurements for designing PAs.

Linking measurements to a circuit simulator creates powerful design opportunities. By employing a simulator, the data can be further reduced to insightful information and utilized for PA circuit design. One analysis approach is to employ an optimizer to search for specific performance conditions. For example, suppose it is desired to find the impedance locus that conform to concurrent power-out, efficiency, and linearity goals versus frequency. An optimization can be established to perform this task using the circuit simulator. Figure 7 is a schematic excerpt showing how three variable equations (output power, third-order intercept, and efficiency) and goal statements are established in ADS. Variable expressions are linked to the goal control blocks as well as the DAC, which provides association to the measured data. During each iteration, the DAC reads and interpolates the performance values based on the present independent variable values. In this case, R_p and C_p independent variables (representing the load) are allowed to vary in the optimization (for simplicity, assume the other independent variables are fixed). When properly configured, the goals, equations and DAC will establish an error function. Since the DAC can interpolate the dependent variables, the equations behave as continuous functions. The optimizer therefore drives the R_p and C_p values continuously until an error function minimum is achieved.

The complexity of the example can be expanded by allowing the other independent variables to vary in the optimization (and allowed to take on different values at different frequencies). These other independent variables can also be plotted versus frequency.

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Figure 8 shows the impedance locus presented to the output required to meet the three performance criteria based on an optimization. In this optimization, the drive-power and bias current were also allowed to vary; however the supply voltage was held constant. These other independent parameters also can be plotted along with the high-level responses after optimization. This optimization could be further tailored to weight each different performance goal differently or attach more importance to specific parts of the band. A further embellishment is to parameter sweep the goal specifications resulting in a family of gamma plots. The analysis described here might be one of the first steps a user would perform in the EDA simulation environment to understand the target impedances the output matching network must achieve. The next step would be to design and optimize an output network using this response as a target.

Previous analysis provided the output load to achieve the specified performance goals. A network must be designed that closely mimics this response. In the traditional disconnected process, the impedance locus would be the only data the designer has available within the simulation environment—providing he was skilled enough to have hand selected the best points from contours or tabular data. With the system described here, however, the full load-pull space including impedance with corresponding performance is available. Using Fig. 8 as a guide, an initial topology and component values are chosen usually through the Smith Chart or matching synthesis program. Once the topology and values are established, a circuit optimization is conducted with the element values driven by performance specifications, not abstract impedances. Contrast this new method with the traditional approach where only a handful of select states are available. With prior methods, EDA optimization goals are strictly impedance based where the designer attempts to optimize for the best match. No insight is provided on high-level performance—a problem when the optimized response is not identical to the selected values. The new method with the multidimensional load-pull space integrated in the EDA simulator takes a different approach to optimization.

High-level performance metrics and their corresponding impedances are accessible to the simulator and enable the designer to establish network optimization using these high-level specifications as goal drivers. As illustrated in Fig. 9, this is accomplished by driving the candidate output matching network with an AC source and utilizing voltage and current probes formulating an admittance calculation looking into the candidate network. Through the auxiliary equations, the driving-point admittance is converted to equivalent R_pC_p. Values of R_p and C_p are then linked into the DAC element; steering the value of the high-level performance metrics. The optimization process is iterative and an error function based on the goal blocks is calculated after each iteration and drive tunable circuit element values. Circuit-element changes affect driving point admittance and close the optimization loop. At the conclusion of the optimization, an impedance response, performance responses, and optimized circuit-element values are available. Network optimization is based on high-level performance goals. Furthermore, the optimization used the full space of load-pull data to arrive at a solution—not a group of heuristically selected points. The results of a sample optimization are shown in Fig. 10.

The amplifier design may proceed along a number of avenues at this point. A statistical Monte Carlo run can be established by allowing the circuit elements to vary and observing histograms of high-level performance. The input match can be designed using similar optimization techniques since the device input impedance is a dependent load-pull variable. Once the I/O matches are designed, a module drive-up performance is possible referencing the load-pull data. Integrating the load-pull measurements into the EDA simulation environment clearly opens up new, cycle-time-saving simulation possibilities.

The RF power designer now has a more comprehensive toolbox at his disposal. Linkage of a load-pull database to a circuit simulator effectively creates a behavioral model. The model can be instantiated into the EDA environment just like any other primitive model and enables rapid up-front architectural decisions leading to circuit and module designs. The EDA utilities discussed here are just a few of the design steps in the development process flow. Small signal s-parameters over multiple bias conditions can be added to the library database. With these large and small signal data, the entire PA design flow can be implemented into a "Design Guide." The design guide concept is a series of development steps required to design a specific application (i.e., a PA). When an ADS customized design guide is created, these steps become sequential pull-down menu selections integrated into the design environment. This promotes design consistency and eliminates much of the tedium in setting up, formatting, and presenting simulation information. It also provides a consistent interface that can be easily archived and navigated for reuse opportunities.

REFERENCES

1. "What's New in 2002?" Applied Wave Research, El Segundo, CA, www.mwoffice.com.
2. "Advanced Design System 2002 Circuit Component Systems Models," Agilent Technologies Manual Set, February 2002, p. 296, www.agilent.com.
3. "Precision Microwave Instruments and Components Catalog," Maury Microwave Corp., Ontario, CA, 2001, p. 64, www.maurymw.com.
4. "The CCMT-µW-PADS Work Station," Technical Note 1-93, Focus Microwaves, Inc., Dollard-des-Oreamux, Quebec, Canada, www.focus-microwaves.com.
5. "WinPADS, A Power Amplifier Design Software Using Load-Pull Contours," Product Note 56, Focus Microwaves, Inc., Dollard-des-Oreamux, Quebec, Canada, www.focus-microwaves.com.