How to Optimize Your SerDes Design During the Pre-layout Phase

Sponsored by Keysight Technologies

    Date & Time

  • Thu, September 25, 1:00pm EDT

    Event Type

  • Live Webinar

Speakers

Colin Warwick

Dr. Colin Warwick
High-Speed Digital Product Manager
Keysight EEsof EDA

Description

Why this Webcast is Important:
In the era of receiver equalization, older stackup and controlled impedance line design tools are obsolete because the metrics that output (frequency response) are irrelevant. The metric that matters today is the post-equalization eye opening. In this webcast we will show you how to optimize the pre-layout design using a PCI Express transmitter, channel, and receiver as an example.

Who should view this webcast:
Signal integrity engineers designing controlled impedance lines for multigigabit SerDes such as PCI Express.

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