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Date & Time
- On-Demand Webinar
R&D Section Manager
Why this Webcast is Important:
DDR electrical compliance testing is required for memory controllers and DRAMs to comply with the JEDEC specification and to be interoperable among vendors. The increasing demands of higher speed and density, lower power and cost present many challenges to DDR designers. This webcast discusses Agilent DDR3 and DDR4 compliance test applications using both pre-silicon simulated waveforms and post-silicon measured waveforms, with emphasis on correlating simulation with measurement. We will describe a methodology for simulating the full path from memory controller to DRAM solder ball. A simulation-measurement correlation methodology called “Waveform Bridge” is discussed where DQ and DQS waveforms in both pre-layout and post-layout simulations are used to feed a DDR compliance test app.
Who should view this webcast:
Signal Integrity Engineers, High Frequency Measurement Engineers, AMI model developers. This webcast is intended for DDR designers involved in reference designs, packaging, channel designs and board level verification.