32-nm SOI CMOS Process Enables 210-GHz Transceiver

May 7, 2014

A research group out of California has developed a 210-GHz CMOS fundamental transceiver on a 32-nm SOI CMOS process.

To implement inter-chip communications in the millimeter-wave frequency ranges, clever circuit techniques and high-performing semiconductor processes are critical. Using a nanoscale silicon-on-insulator (SOI) CMOS process, for example, a 210-GHz fundamental transceiver with on-off keying (OOK) modulation has been designed and tested by Zheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, and Payam Heydari from the University of California.

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The on-chip electronics and antenna of the 210-GHz OOK transceiver allow for short-range interchip communication with over 10-Gbps throughput.

Here, a 2-by-2 combining spatial array constructed of double-stacked and cross-coupled voltage-controlled oscillators (VCOs) is used to generate the OOK modulated signal. An array of power amplifiers (PAs) with a balun-based differential power-distribution network drives the 2-by-2 antenna array transmitter (Tx). The transmitted signals are detected and demodulated by a non-coherent receiver (Rx) using direct detection with a single on-chip antenna, low-noise amplifier (LNA), and power detector.

The Tx is capable of an equivalent isotropically radiated power (EIRP) figure of 15.2 dBm with fully driven PAs. The LNA performed with 18 dB of gain at 210 GHz with over 15 GHz of bandwidth. Given these metrics, the communication link could reach 10 Gbps using root-raised-cosine (RRC) filtering. With ideal filtering, the theoretical data rate that can be reached is 20 Gbps. See “A CMOS 210 GHz Fundamental Transceiver With OOK Modulation,” IEEE Journal of Solid-State Circuits, March 2014, p. 564.