ADCs Enable Direct Sampling To 2.7 GHz

The capability of the ADC12Dxx00RF ADCs to sample high input frequencies to 2.7 GHz and higher allows elimination of one or more IF stages in high-frequency receiver designs.

Digitization of RF/microwave signals within a receiver usually takes place at intermediate frequencies (IFs). But with the ADC12Dxx00RF family of analog-to-digital converters (ADCs) from National Semiconductor, some receivers may no longer require an IF section. These high-resolution 12-b ADCs can directly sample input frequencies to 2.7 GHz and beyond, changing the way that RF engineers design radio front-end sections. With sampling rates to 3.6 GSamples/s, these ADCs will certainly have an impact on a wide range of commercial, industrial, and military applications, including cellular base stations, microwave backhaul systems, and software-defined radios (SDRs).

The high-frequency operation of these new ADCs allows radio designers to rethink their circuitsperhaps eliminating an entire IF and frequency-downconversion section and all related components, including filters, amplifiers, and frequency mixers (see figure). The data converters are pin-compatible with the firm's ADC12D1x00 and ADC10D1x00 families of ADCs, for virtual plug-in upgrades to existing circuit and system designs based on those earlier converters.

The five new ADCs in the product family (see table) offer performance levels ranging from two channels at 500 MSamples/s to a single channel operating at 3.6 GSamples/s, all with 12-b resolution. The devices feature dual-ADC internal architectures that allow the twin ADCs to operate in two-channel mode or tightly synchronized in interleaved single-channel mode. The fastest member of the new product line is model ADC12D1800RF, with single-channel interleaved sampling rate of 3.6 GSamples/s and sampling rate of 1.8 GSamples/s per channel in dual-channel mode. As with the other ADCs, it features excellent linearity, with third-order intermodulation (IMD3) performance of -64 dBc when evaluated with a 2.7-GHz input signal at -16 dBm full scale. This data converter also delivers a typical noise floor of -155 dBm/Hz. When tested in dual-channel mode at 1.8 Gsamples/s per channel, the signal-to-noise ratio (SNR) is typically 57.7 dB and the spurious-free dynamic range (SFDR) is typically -70 dBc. The converter offers 9.2 b effective number of bits (ENOB) and consumes about 4.4 W power (2.2 W per channel).

The outstanding linearity of these direct RF-sampling ADCs across all frequencies relaxes the margins required on other receiver components, further cutting costs in a system design. The converters feature flexible LVDS interfaces with multiple SPI programmable options. The ADCs are supplied in pin-compatible, thermally enhanced 292-ball ball-grid-array (BGA) packages. They are designed for operating temperatures from -40 to +85C and are well suited for applications in cellular backhaul equipment, cellular base stations, SDRs, radar and signal-intelligence (SIGINT) receivers, and test-and-measurement equipment.

National Semiconductor Corp.
2900 Semiconductor Drive, P. O. Box 58090
Santa Clara, CA 95052
(408) 721-5000