Microwave Transistor-Parameter Trade-offs in Circuit Design: Part 3

Fig. 1.Transistor-package circuit. This representation clearly shows that packaging has a significant effect on the performance of a transistor at microwave frequencies.

Fig. 2. Package gain-bandwidth vs collector current for various dc betas. A high-beta transistor with a low narrow base will exhibit current crowding at low current levels.

A high-beta transistor with a narrow base will exhibit current crowding at low current levels. The relationship between current gain-bandwidth product and collector current for different h_FE levels (for a resistor-stabilized device) is shown in Fig. 2. The current gain of the packaged device is considerably less than the current gain of the device itself. This is because of degeneration cause by the resistance introduced into the emitter structure. At a current level of about 1.1 A a sharp dropoff exists in hf current gain (as was true of dc current gain) and this is a result of current crowding. The maximum current rating of a transistor is specified in an area where the hf and lf current gains are still useful. This explains the 1.5-A max collector current rating for this transistor.

To keep within the most linear portion of the transistor characteristics, the average current within the device should be held no greater than 1 A. It can be seen that a low-h_fe device has less percentage change in hf current gain-bandwidth product than a high-h_fe device. This is also true for h_FE (or dc beta). The other variables which affect h_fe are primarily resistors introduced into the emitter circuits of resistor-stabilized transistors, and current distribution for equivalent betas. The transistors represented in Fig. 2 have been chosen for equivalent emitter resistance to eliminate this effect on measurement. Other important correlations to h_FE further validate the concept of what is happening in the base under the emitter.

Output admittance (y_oe) to h_FE relationship

Fig. 3. Output impedance vs collector current curves show that the higher the dc beta the lower the output impedance, particularly at low values of collector current. The effect is not great, however.

It is important to note on these curves (which represent small-signal measurements of parallel output resistance) that output resistance decreases significantly as the collector current is increased. This provides a clue that the output resistance will be significantly lower in a large-signal circuit of an rf power amplifier than for the small-signal case or where the transistor drive level is low. Thus, the harder a transistor is driven, the lower the output impedance will become. Measurements of large-signal output impedance should bear this out. Output capacitance is fairly constant with current swing but not with voltage.

Collector breakdown-voltage differences will also affect the output impedance. For a single-type transistor, one with a higher BV_CBO than another (and thus a higher resistivity) will have a lower output capacitance and subsequently a somewhat higher output impedance. The trade-off, however, is that the higher the collector-base breakdown voltage (and thus the resistivity of the silicon material) the lower the saturated power-output capability of the transistor. This condition increases the saturation voltage level and reduces efficiency as a transistor multiplier.

Input impedance (Z_in) to h_FE relationship

Fig. 4. Input circuit representations. Where the input capacitance is large, as for high-power transistors, the general circuit (a) can be simplified to that at (b).

The input impedance of a transistor at high frequencies can be represented by the simple circuit in Fig. 4a. Assuming the input capacitance is large, as for a high-power rf transistor, the circuit can be reduced to that of a series inductance and a base resistance shown at b. The input capacitance decreases as the dc beta of the device is increased as shown in Fig. 5. Therefore, the hf input inductance becomes effectively smaller as the dc beta becomes greater. This is because the capacitive reactance will be larger and cancel out more of the package and circuit inductance. This is shown in Fig. 6 where the effective small-signal series inductance decreases as the dc beta increases. The large-signal value will also be different from the small-signal value. The inductance due to the package itself is of fixed value.

Fig. 5. Input capacitance vs dc beta. The capacitance decreases with increased beta, which means that the hf input inductance (Fig. 4b) becomes less as dc beta increases.

Fig. 6. Series input inductance vs dc beta (small signal). This phenomenon follows from the effect shown in Fig. 5 for input capacitance vs dc beta.

A high-dc-beta unit would be expected to have a higher base resistance since the lateral sheet resistance of the base under the emitter would be higher. The effect is fairly pronounced as shown in Fig. 7. The base resistance can increase by as much as 25 percent over the beta range of any transistor type. This is a small-signal base resistance and is lower in a large-signal condition.

Fig. 7. Base resistance vs dc beta. The lateral sheet resistance of the base under the emitter increases with dc beta.

Trade-offs

Fig. 8. Series base resistance vs input current. Note that lower dc-beta transistors have less variation in input resistance with current.

The input impedance should have less variation with collector current (or emitter current) if the device has a low dc beta. In Fig. 8 the series base resistance, r_b, (or real part of h_11e) has less variation with current for a low h_FE transistor. A definite similarity of the impedance-vs-current curve to the h_fe-vs-current curve exists. The same rapid change in resistance is observed in the same current region, as for dc beta and for h_fe. It is also apparent from these curves that the large-signal impedance will be much lower than the small-signal value. This impedance in a tuned circuit is also affected by the stored charge and how the charge is drawn out of the device in the “off” part of the drive cycle. This would have the effect of lowering the input impedance still further. These curves show that the harder a transistor is driven (such that the average and peak currents become higher), the lower the input resistance. Large-signal impedance measurements show this to be true.

The series inductance, L_s, would also be expected to show variations with collector current, since the input capacitance changes with current. Typically, the input capacitance of a transistor increases as the collector current increases. The input capacitance would also be affected by the current pinch-off effect. Also, one would expect a more rapid input-capacitance change in the same areas where there are rapid changes in the input resistance, h_FE, and h_fe. Since capacitance increases with current level, the effective series inductance would be expected to increase likewise. This is because there will be less capacitive reactance to subtract from the package inductance. The theory is borne out in practice as shown in Fig. 9, where a larger change in input inductance occurs for a high-h_FE device than one of low h_FE. Both curves show a tendency to have rapid changes in series inductance above 1.1 A where this correlates with the same rapid changes in other parameters and in h_FE itself. Inductance also increases with current. This corresponds with an increase in input capacitance with current. One must examine the combined effect of L_s and r_b to see how the input circuit Q and package bandwidth are affected by current and h_FE. Again, it should be noted that the large-signal input inductance will depend on the stored charge of the transistor and the class of operation. Thus, these curves can only give an indication of which way the values will go. Typically, the large-signal values of these curves will be somewhat different from the high-current values.

Fig. 9. Input inductive reactance vs collector current for low- and high-dc beta transistors. The low-beta transistor has less over-all reactance variation than the one with a high beta.

Package Q and sensitivity to series lead inductance

The bandwidth sensitivity factor is defined as:

This sensitivity factor gives a relative measure of the bandwidth lost when a series inductance is added using the small-signal short-circuit impedance measurements as the criteria. It can only be a relative factor, because bandwidth is also significantly affected by changes in input impedance caused by the load on the collector.

Fig. 10. Bandwidth sensitivity vs dc beta. One would choose a high-beta transistor for a high-input impedance for ease in matching and for lowest input Q.

Because the input impedance is a function of the transistor’s dc beta, it is possible to plot a range of values for the sensitivity factor S_B vs h_FE, using the measured values of the small-signal input parameters. This plot is shown in Fig. 10. Over the normal beta range for a given device type, the sensitivity factor can vary all the way from 15 Mc/nH to 90 Mc/nH at the high-beta end. There is a significant trade-off here. One would like to choose a high-beta device for a high-input impedance for ease of matching and for lowest input Q.

This creates a problem in that the bandwidth sensitivity is a maximum for a change in series inductance brought on by packaging or placement of components. A middle-of-the-road compromise is to choose a mid-range beta. More work will be required with actual broadband loads and large-signal input-impedance and bandwidth measurements to determine what the actual sensitivity factor is in a direct circuit operating mode. But the small-signal analysis indicates the direction of the tradeoffs. The small signal package Q is:

Package Q is dependent upon the h_FE of the device. A typical median-range plot (Fig. 11) of many device measurements shows the approximate variation in package Q with h_FE. Because of differences in resistor stabilization values, transistor resistivity, and uniformity of current and power distribution over the device, package Q can vary over quite a broad range either side of this median curve for a given h_FE.

Fig. 11. How package Q varies with dc beta. Factors that affect this curve are resistor stabilization values, transistor resistivity and uniformity of current and power distribution over the device.

Fig. 12. Variation of package Q with collector current. Note rapid change in Q above the 1.1-A level.

Package Q is also a function of the collector current as shown in Fig. 12, and one would expect it to change even more rapidly as other parameters change at the same time.

Not the sharp change in package Q above the 1.1-A level for a 3TE440 transistor.

Large-signal input impedance measurements

Fig. 13. Large-signal input-impedance test setup for 400-Mc measurement. Test results are shown in Fig. 14.

Fig. 14. Large-signal input-impedance curves. Note that the large-signal r_b shown here is considerably lower than for the small-signal case shown in Fig. 8.

Power gain as a function of transistor parameters

A significant trade-off between power gain and the other required transistor parameters exists for each particular circuit operation. Power gain is a function of frequency, and at high frequencies approximates 6 dB/octave roll off. The lower the frequency where a transistor is used, the greater the sensitivity of power gain to h_FE. At quite low frequencies, as expected, power gain is controlled more by the h_FE of a transistor than by other basic parameters. A 400-Mc transistor, for instance, demonstrates this phenomenon as shown in Fig. 15, when operating at the lower frequency of 250 Mc. A large lot sampling of the devices at this frequency gives the distribution shown. Obviously, low-beta transistors have significantly lower gain than those with high beta. The range is roughly from 6 to 10 dB for the normal h_FE range of a device family. Thus, there is a significant trade-off between the power gain that can be expected and the other required device parameters which correlate to h_FE.

Fig. 15. Power gain vs dc beta. At lower microwave frequencies, the power gain is controlled more by h_FE than by other parameters.

In addition to correlation of power gain to h_FE, it would also correlate to V_CE(SAT). This is especially true where high V_CE(SAT) devices are caused by either non-uniform current distribution or (for resistor stabilized devices) higher value resistors in the emitter.

Saturated power output trade-offs

Saturated-power output capability is a significant and often overlooked characteristic of a power transistor. Among those presently marketed by many manufacturers, there is a wide range between the saturated-power-output capability and the specified power-output capability. Many designers tend to design around the saturated-power output if they can obtain this saturated power output without exceeding the dissipation limits of the transistor. In addition, the power a transistor dissipates under a high VSWR load condition is partially a function of saturated-power output capability. A significant trade-off exists between saturated power output capability and h_FE. This is because of the current pinch-off effect under the emitter as previously described, where current peaks are more difficult to obtain with a high h_FE.

Fig. 16. Gain saturation curves at 330 Mc. The lower dc beta transistors show significantly higher power gain.

Thus, device saturation would be expected at a lower level. Measurements of a device family, selected such that other parameters which affect saturated power output are equivalent in all devices at 330 Mc, are shown in Fig. 16. Here, a low h_FE device has a significantly higher output level than one having high h_FE. Also, note the differences in power gain as a function of h_FE.

Another trade-off in the saturated-power output is with V_CE(SAT). The higher the V_SAT the lower the saturated-power output for a similar h_FE. Table 1 shows roughly the trade-off between V_CE(SAT) measured at dc and at saturated P_OE (the rf V_SAT will be considerably higher but will also correlate). This is done on a high h_FE unit to emphasize the correlation. A lower h_FE device would not be quite as sensitive to the trade-off.

Table 1. Correlation of V_CE(SAT) to P_OE(SAT) (For h_FE = 60-65 units)

Saturated-power output would also correlate to the BV_CEO transistor breakdown voltage because a high BV_CEO would indicate a high resistivity collector. This, in turn, would indicate a higher V_SAT or a lower saturated-power output. However, as previously noted, a high BV_CEO unit would have less C_OB and more power gain. The trade-off between all of these parameters becomes somewhat complex.

Thermal effects, resistor stabilization and trade-offs

Fig. 17. How thermal resistance varies with collector current. The effect is nonlinear and much lower at low-current, low-voltage levels.

Because thermal resistance is a function of V_CE and I_C, it would be expected that the safe operating area under pulsed conditions would be a function of these parameters as well as the thermal time-constant of the device itself. If the safe-operating area under pulsed conditions is defined as that point at which some part of the junction area of the transistor reaches 200° C and pulsed measurements are then taken, safe operating curves are shown in Fig. 18, result.

Fig. 18. Safe-operating pulse conditions for a typical microwave transistor. These curves are based on the transistor junction area not exceeding 200° C.

VSWR capability, or the ability of a transistor to withstand a high VSWR load (i.e., approaching or equal to an open- or short-circuit condition) is an important consideration and correlates to some of the other transistor parameters. High-VSWR capability can relate closely to a transistor’s dissipation capability. Through part of the VSWR phase angle, the transistor must dissipate more power than in matched condition. Thus, a resistor-stabilized device, or one with a higher safe-operating area, can withstand this VSWR load better. The other trade-offs to obtain this capability are already apparent. Also, a device with a lower saturated-power output tends to limit its peak current more. Thus its total power dissipation is somewhat less. This is another direct trade-off between VSWR capability and the device itself. In the other phase of VSWR, a high-voltage, low-current condition exists on the collector. Here, a high-voltage break-down requirement and a sustained-high-current capability in avalanche are important. The trade-offs of high-voltage capability have already been discussed. However, high-avalanche sustaining-current capability has been difficult to relate directly to other basic device parameters that a circuit designer measures. It must be designed into the transistor.

Fig. 19. Basic VSWR test circuit. Using this test setup one can measure the variation in transistor power dissipating, power output and collector current as a function of phase length between output circuit and load.

A typical variation in transistor power dissipation, power output, and collector current as a function of phase length between the transistor-output circuit and the load can be measured as shown in Fig. 19, with results as shown in Fig. 20 when adjusted for line losses. These curves illustrate how the phase between the output circuit and the VSWR load is important in determining what is happening at the transistor.

Fig. 20. Test results from setup of Fig. 19 show how the phase between output circuit and load is important in determining events at the transistor itself.

Summary