RF chipsets are at the heart of WiMAX solutions for base-station hardware and customer-premise equipment (CPE). The TRF1xxx chipsets from Texas Instruments (www.ti.com), for example, house integrated synthesizers to realize a superheterodyne architecture. To achieve optimal channel resolution, these devices must be tied to an 18-MHz reference frequency. In some systems, however, the synthesizer reference frequency must be synchronized to a systemreference frequency that may not be an integral multiple of 18 MHz. In "Synchronizing WiMAX Synthesizer TRF1x21/TRF1x12 to Arbitrary Reference," Texas Instruments presents the circuitry that is needed to synchronize the 18-MHz reference to an arbitrary system-reference clock.
The five-page application note begins by showing a block diagram of the TRF1xxx chipset. A reference frequency of 18 MHz corresponds to the frequency resolution of the S-band voltage-controlled oscillator (VCO) of 1 MHz and 62.5 kHz for the ultra-highfrequency (UHF) VCO. Any deviation from 18 MHz will result in fractional step changes in the synthesizer and inability to properly tune.
Because the system reference frequency is considered fixed, it cannot be changed by designers. Additional components are, therefore, required to provide the appropriate 18-MHz reference. For an example, the note points to the CDCM7005 differential clock driver and clock distribution chip. A clock distribution chip is required on base-station systems because clocking devices need to be synchronized. Yet they also must be clocked at different multiples of each other. To synchronize the system-reference frequency, the CDCM7005 relies on a voltage-controlled crystal oscillator (VCXO).
Usually, additional circuitry will be required to provide the 18-MHz reference that is synchronized to the system clock. The application note suggests that a single phase-locked loop (PLL) should be introduced with an additional VCXO at 18 MHz. Another concern is the phase frequency detector (PFD), which must be set to a relatively low value to keep the divider registers within range. For an 18-MHz oscillator and 10-MHz reference, the PFD frequency is set to 100 kHz. Keep in mind that other parameters related to the oscillator gain and charge-pump current may be different for a crystal oscillator compared to a traditional VCO. The PLL filter must, therefore, be designed to provide sufficient attenuation of PFD spurs and sufficient phase margin in the loop for stability. The note includes a phase-noise comparison of the TCXO versus the TRF3750 and VCXO reference.
Texas Instruments, Inc., P.O. Box 660199, Dallas, TX 75266; (972) 995-2011, Internet: www.ti.com.
