Download this article in .PDF format
This file type includes high resolution graphics and schematics.

To overcome these limitations of traditional low-voltage, low-power mixer approaches, a mixer was designed with bulk-injection, DTMOS, and switched-biasing techniques for applications from 0.6 to 11.0 GHz. The bulk-injection technique combines the RF transconductance stage with the LO switching stage to reduce the number of stacked transistors, providing flat conversion gain over a wide frequency range with low DC power consumption. Unfortunately, the bulk-injection approach exhibits relatively high NF. To reduce flicker noise and white noise, a switched-biasing technique with DC level shifting circuits was adopted in the new mixer design.

Figure 1 shows a conventional Gilbert-cell double-balanced mixer. It contains four stages: tail current source (transistor M8), RF transconductance stage (transistors M1, M2), LO switching stage (transistors M3-M6), and output load stage (resistor RL). Devices M1 and M2 transconduct differential RF input signals into small-signal drain currents. These currents are then switched by transistors M3-M6 as a function of the local oscillator (LO) signal, thus performing performs frequency conversion.

1. This schematic diagram represents a conventional Gilbert cell double-balanced mixer.

For the circuit of Fig. 1 to operate as intended, the supply voltage (VDD) must be high enough to maintain the tail current source transistor (MB), the RF transconductance transistors (M1, M2), and the LO switching transistors (M3-M6) in saturation, while taking into account the voltage drop across the load resistor (RL). Because of the high minimum supply-voltage requirement in a Gilbert-cell mixer, low-voltage operation is difficult to achieve.

The proposed new mixer is based on the body effect that occurs when a device gate terminal is used as an input signal terminal. To understand this effect, when the gate terminal of a transistor (in a mixer circuit) is fed by an LO signal, the drain-source current, IDS, can be expressed by Eq. 1:

IDS = K(W/L)( VGS - VTH)    (1)


K = a proportionality constant;

W = the transistor gate width;

L = the transistor gate length;

VGS = the voltage between the transistor’s gate and source; and

VTH = the threshold voltage of the transistor.

Since VTH is a function of the voltage between the bulk material and the source, VBS, to a first-order approximation, VTH, can be written in the form of Eq. 2:

VTH(LO) = VTO + γ[2φF - VBS(LO)]0.5 - γ(2φF)0.5    (2)


VT0 = the zero substrate bias threshold voltage, where the typical value of VT0 is about 0.5 V in a 0.18-μm silicon CMOS semiconductor process;

φF = the surface potential; and

γ = the body effect factor.

From Eqs. 1 and 2, the only parameter available to the designer for threshold voltage manipulation is the bulk-source voltage, VBS. The LO signal as a function of bulk-to-source voltage is injected into the bulk of the transistors, and the threshold voltage is then modulated with the LO signals.14 If the gate of the transistor is biased close to the threshold voltage and the LO signal swing is large enough, the transistors of the bulk-injection core stage will turn on and off as a function of the LO signal.

Figure 2 shows the complete circuit diagram of the proposed mixer, with the output buffer and mixer core. The mixer consists of five parts: the switched-biasing stage (containing transistors M1, M2); the bulk-injection core stage (M3-M6); the load stage (M7, M8); the output buffers (M9, M10 and R3, R4); and the DC level shifting circuits (M11, M12 and R1, R2).

2. This schematic diagram represents the proposed mixer.

Download this article in .PDF format
This file type includes high resolution graphics and schematics.