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Other mixer designs have employed the bulk-injection concept. The circuit in ref. 15 applies the RF signal to the transistor bulk portion and the LO signal to the gate; this produces lower gain, since the bulk-source transconductance is much lower than the gate-source transconductance. The design in ref. 16 uses PMOSFETs (for isolation), as the process used for that design did not support the deep n-well option.

In contrast to a conventional Gilbert-cell mixer, the bulk-injection core stage merges the RF transconductance stage with the LO switching stage. Since it has one less stacked stage than a Gilbert-type mixer, the proposed mixer can operate with a lower supply voltage. In addition, the gate-source voltage of the core transistors (M3-M6) is lower than the threshold voltage (VGS = 0.45 V) in order to operate in the subthreshold region, resulting in low current dissipation.

The PMOS transistors (M7, M8) and their high output impedances are used as an active load to transfer current to voltage for the mixer’s intermediate frequency (IF) output signals. Moreover, the PMOS active load can reduce the alternating current (AC) flow through the mixer core and lower the voltage drop on the active load. The supply voltage (VDD) can also be lower; in this mixer, the optimum value of VDD is 0.7 V.

The buffer stage consists of two common-source NMOS amplifiers, defined by M9, M10, R3, and R4 in Fig. 2. The buffer stage achieves the impedance matching for driving a 50-Ω load and offers sufficient power gain to maintain positive gain in the new mixer design.

A mixer following a low noise amplifier (LNA) is an important building block in a wireless communications system, and a mixer with high noise will increase the noise figure of the overall system.17 In addition to white thermal noise, MOS transistors are notorious for flicker (or 1/f) noise. In general, the 1/f noise performance of a mixer is primarily determined by the LO switching pairs. Conventional flicker-noise-reduction techniques generally lead to higher power consumption.

For the proposed mixer, a switched-biasing technique is employed to improve the mixer’s noise performance and reduce the power consumption. This approach has been applied to lower the flicker noise is a switched biasing technique at the tail current circuit; it was initially adopted to improve phase noise in voltage-controlled-oscillator (VCO) circuits.18

The switched-biasing technique tackles the 1/f noise problem by cycling a MOS transistor between strong inversion and accumulation regions. The technique reduces both flicker and white noise. When the flicker noise from an MOS transistor that is due to the current source can be reduced, the NF of the mixer can be improved. Additionally, by using self-biasing with the drain output signal of transistors M7 and M8 to drive the tail current transistors, the mixer does not require supplementary bias circuits. It is capable of reducing power consumption, as well as current source variations from supply-voltage and temperature effects in bias circuits.

In general, a low NF is most critical for low input power levels. However, any NF improvement from the switched-biasing technique will be minimal under low signal power. As Fig. 2 shows, DC level shifting circuits are composed of M9, M10, R1, and R2 to provide the tail current transistors; a proper gate-source voltage makes the overdrive voltage (VOV = VGS - VTH) very small for the symmetric switching operation with a small output swing.

Figure 2 also shows that transistors M1 and M2 are dynamic-threshold-voltage MOS (DTMOS) devices, a configuration obtained by tying the gate and the bulk of a MOSFET together. In this approach, the threshold voltage of the MOS transistor is a function of its gate voltage—i.e., as the gate voltage increases, the threshold voltage drops, resulting in much higher drive current than in a standard MOSFET.19

The DTMOS approach supports low-voltage applications. A DTMOS device can have a high threshold voltage at gate-to-source voltage equal to zero. Therefore, the leakage current is low. At gate-to-source voltage equal to VDD, the threshold voltage is low and the device can achieve high speed. This dynamic variability is beneficial for low power consumption at very low voltage.

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