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A balanced design (push-pull) amplifier configuration also benefits from higher output impedances. Two +48-VDC devices, each with 12.5-Ω load resistance at 90 W output power, present an impedance of 25 Ω to the primary in a push-pull configuration. Figure 4 shows how four devices can be set in a balanced push-pull configuration combined using coaxial sleeve baluns, allowing operation over a wide bandwidth.2 Higher output impedances enable other transmission-line transformer and combinational networks. Depending on the frequency band and required bandwidth, many tailored topologies are available for consideration.3

High-Voltage GaN-on-Si Devices Deliver High Power, Fig. 4

Power amplifiers (PAs) for wireless infrastructure applications with wideband-code-division-multiple-access (WCDMA), Long Term Evolution (LTE), orthogonal-frequency-division-multiplex OFDM, and other high-peak-to-average (PAR) waveforms face a real challenge. Achieving even modest amplifier efficiency is difficult when the RF amplifier is appropriately sized for peak power levels that are 8 to 10 dB higher than the average power level.

Envelope tracking (ET) is one of several effective techniques to address this issue. ET raises and lowers the drain voltage to follow the instantaneous peak amplitude of the device, effectively adjusting the compression point of the amplifier in real time to increase amplifier efficiency (Fig. 5). A peak-to-average ratio (PAR) of 10 dB, or 10×, implies a voltage ratio of approximately 3:1. This is a typical ratio seen in commercial systems.

High-Voltage GaN-on-Si Devices Deliver High Power, Fig. 5

For ET with +28-VDC devices, the drain supply typically varies between +10 and +30 VDC. This presents a problem for both GaN and LDMOS devices at the low end of this range because small-signal gain becomes nonlinear as a function of supply voltage. Above about +12 VDC, the gain increases linearly with voltage, but below +10 to +12 VDC, the gain enters a nonlinear region and can drop several dB below its nominal level at higher voltages. The statistical nature of a high-PAR signal implies an ET PA operates in this low-voltage region most of its time, thus encountering this unwelcome nonlinear gain condition. With a +48-VDC device, a typical ET system varies the drain between +20 and +60 VDC and the minimum voltage remains well above the onset of the nonlinear gain condition. 

A +48-VDC GaN device provides an additional benefit over an LDMOS device because of the reduced COUT of the device. As mentioned previously, the higher COUT of LDMOS devices mandates internal pre-matching on the output to provide more friendly terminal impedances. The chosen topology for this output pre-match is usually a shunt-L match in the RF path. The shunt-L is designed to resonate with COUT to improve the terminal impedance.

All active transistor devices have terminal capacitances that vary versus applied voltage. When the drain supply voltage is modulated to follow the signal envelope, the drain-to-source capacitance (CDS) also varies and the shunt inductance (L) resonance is impacted, changing the terminal impedance of the device in real-time with the drain voltage. This leads to a nonoptimal impedance match for ET applications.5

In addition, because the shunt-L match requires a large shunt DC-blocking capacitor, there is additional strain on the envelope modulator design (Fig. 5), which is already challenged to swing large voltages with high current capability at high data bandwidths. The large blocking capacitor prevents the envelope modulator from being able to raise and lower the supply voltage in time with the modulation bandwidth. The low COUT of GaN devices means this matching topology is not needed, making +48-VDC GaN devices inherently optimized for ET applications.

A transition to a +48-VDC drain supply may raise concerns given the higher voltage. Although there may be thoughts that a higher voltage causes additional stress and lower reliability, this has not been found to be the case. Between +28 and +48 VDC, no difference has been found in DC reliability studies, with both voltage optimized technologies achieving 1 × 106 hours mean time before failure (MTBF) at a junction temperature of +200°C. It is important for RF system design engineers to realize the connection between junction temperature and device reliability. The key to reliable design is maintaining device junction temperature below specified limits. Designers need to monitor ambient temperature and operating conditions (power dissipation) to guarantee reliable operation.6

Compared to +28-VDC devices, +48-VDC devices are physically smaller for a given RF power rating and the advantages of performance come primarily from this difference. This flows down into every aspect of the device, from the difficulty and performance of the impedance match, to the usable bandwidth and relative achievable performance.

Legacy commercial and military RF systems are well rooted in the use of +28-VDC power-amplifying devices. While LDMOS and GaN device suppliers will continue to support and increase +28-VDC offerings, new systems with the flexibility to do so should consider higher-voltage devices. The +48-VDC GaN-on-Si devices offer compelling advantages for those willing to consider this option.

Raymond A. Baker, Field Applications Engineer

Walter H. Nagy, Principal Engineer

David W. Runton, Vice President, Engineering

Robert A. Sadler, Principal RF Applications Engineer

Nitronex Corp., 523 Davis Dr., Ste. 500, Morrisville, NC 27560; (919) 807-9100, FAX: (919) 472-0692.

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