Designers of silicon-on-sapphire (SoS) circuits can now expect easier times when working with Sapphicon Semiconductor's SoS process, thanks to new process design kits (PDKs) announced by electronic-design-automation (EDA) supplier AWR. The PDKs are based on AWR's Analog Office RFIC design software and support Sapphicon's quarter-micron SoS processes with PDKs in the works for Sapphicon's half-micron SoS CMOS processes. The SoS process is ideal for high-frequency RF and mixed-signal designs requiring low power consumption. According to Yash Moghe, Sapphicon's Design Engineering Manager, "A key aim is to develop highly accurate models for transistors and passives such as spiral inductors at frequencies up to 40 GHz. Analog Office software enables us to accurately model active devices, passives, and interconnects on SoS so that our customers realize first-time-right designs."