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Mixer linearity is critical to modern communications systems, especially for ultrawideband (UWB) applications, but requires imaginative circuit-design approaches. One novel double-balanced-mixer circuit employs a source degeneration common-source topology where four tail current sources are used as degeneration resistors to improve circuit linearity. To minimize power consumption while operating on a low supply voltage, bulk-injection and forward-body-bias techniques are also employed in this design.

This double-balanced mixer covers 1.5 to 11.5 GHz with conversion gain of 6.0 to 7.2 dB. It achieves single-sideband (SSB) noise figure of 18.4 to 20.5 dB with an input third-order intercept (IIP3) of about +1.0 to +6.84 dBm , at the same time consuming only 0.46 mW power from a +0.75-VDC supply voltage.

Increasing demand for low-cost, high-performance portable wireless communications has triggered intensive research on CMOS radio-frequency (RF) front-end circuits. It is well-know that with continuous shrinking of the feature sizes in CMOS devices there is a proportional downscaling in the supply voltage; this yields superior active device high-frequency characteristics in term of power consumption, operating speed, and area.1 However, power consumption remains an issue due to limited battery capacity. Consequently, design for low-voltage and low-power radio-frequency integrated circuits (RFICs) have attracted significant attention and numerous advanced circuit techniques have been proposed in the past few years.2-11

Being widely used in wireless transceivers, the mixer is a crucial component that performs frequency conversion. The conventional Gilbert-type mixer provides high-conversion-gain (CG), low-even-order distortion with superior port-to-port isolation, and is thus beneficial for integrated-circuit (IC) applications. However, due to three-level transistor stacking, the supply voltage available to an active mixer is relatively high. Thus, an IC mixer is inevitably constrained by power consumption.

To satisfy the requirements for low-power operation while maintaining acceptable circuit performance, various design strategies and circuit techniques have been proposed in references 12 through 19. A low-voltage architecture using inductor-capacitor (LC) tanks was adopted in ref. 12. Since the LC tanks require no voltage headroom, this approach allows for a relatively large output swing. Unfortunately, the low Q-value of the spiral inductor limits the operation frequency while still occupying a large die size.

A transformer-based architecture was employed for low power in ref. 13, but the transformer imposed a narrow bandwidth limitation. Another modified mixer structure based on a Gilbert-cell topology was reported in ref. 14, where the mixer core design uses PMOS transistor stacking on the NMOS transistor. However, due to the poor performance of PMOS transistors at high frequency, the operating frequency was limited and the supply voltage was still high. This design was deemed unsuitable for low-power and low-voltage applications.

In order to alleviate the limitations imposed on the supply voltage, a folded-switch topology is proposed to reduce the supply voltage without deteriorating other design parameter.15,16 Nevertheless, the DC current between the transconductance and commutating stages is split—not reused—and may consume an increased power consumption even with a reduced supply voltage.

On the other hand, ref. 17 employs a complementary current-reuse topology with a current-bleeding technique to reduce power consumption. This design approach provides the benefit of reusing DC biasing current and reducing the bias current through the IF and switching stages. However, it suffers from relatively low gain and is usually limited to narrowband operation. Passive mixers offer high linearity and low noise figure with little DC power dissipation,18,19 but they have high conversion loss and also limited isolation between the RF and LO ports. Moreover, large LO signals required to drive passive mixers can significantly increase the power consumption of a receiver system.

What follows is a qualitative description of the mixer’s core operation followed by a detailed look at its performance. Figure 1(a) shows the schematic diagram of the mixer core, which consists of a current source stage (M1), a bulk-driven stage (M2), and a PMOS transistor (M3) as an active load. In contrast to a Gilbert-type mixer, the bulk-injection mixer is based on a four-terminal device where the RF and local-oscillation (LO) signals are applied to the gate and bulk of transistor M2, and the intermediate-frequency (IF) signal is pumped from the drain.20 As a result, the proposed mixer can operate at a reduced supply voltage due to its one less stacked stage compared with a Gilbert-type mixer.

Design A Low-Voltage UWB CMOS Mixer, Fig. 1

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