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Based on Eqs. 7 and 8, it is clear that mixer linearity increases with the output resistance, ron, of transistor M1. However, mixer conversion gain is degraded as depicted by Eq. 4. Hence, a tradeoff between conversion gain and DC power consumption should be reached to achieve relatively high linearity. Figure 3 shows how simulated circuit linearity and conversion gain vary with the value of ron. For this mixer design, the output resistance values of transistors M1 and M2 are 325 and 920 Ω, respectively.

Design A Low-Voltage UWB CMOS Mixer, Fig. 3

Figure 4 shows a complete circuit diagram for the low-power CMOS downconversion mixer. A double-balanced mixer configuration was chosen for enhanced port-to-port isolation. The proposed mixer consists of three parts: a current source stage (M1 through M4), a bulk-driven stage (M5 through M8), and PMOS transistors (M9 and M10) as active loads. In contrast to the cascade structure of a conventional Gilbert-cell mixer, the four bottom NMOS transistors (M1 through M4) are used as degeneration resistors to improve circuit linearity.

Design A Low-Voltage UWB CMOS Mixer, Fig. 4

Meanwhile, a bulk-driven technique is employed for a low supply voltage as presented previously. In addition, a forward body bias technique is introduced to further alleviate the voltage headroom limitation imposed by the use of a low supply voltage. Since a forward body bias voltage (VLO and VB) effectively lowers the threshold voltage, this technique provides the benefit of reducing the operated voltage as well as LO power without compromising device characteristics in term of gain, linearity, and noise figure.

Moreover, current-limiting resistors RB and RLO must be employed at the body terminal to restrict the excessive junction leakage current. Voltages VG and VP represent the gate bias voltage. On-chip capacitors (C1-C2) are applied as DC-blocking capacitors to isolate the input from the DC source. To achieve low-power operation, the three stacked layers of devices are biased in the linearity, subthreshold, and active regions from the bottom up, consuming only about 0.6 mA DC current from a +0.75-VDC supply.

Design A Low-Voltage UWB CMOS Mixer, Fig. 5

The mixer was computer simulated with SpectreRF software from Cadence Design Systems based on chartered 0.18-μm CMOS technology. By employing forward body bias and bulk-injection techniques, the supply voltage falls to +0.75 VDC. The mixer is designed to operate between 1.5 and 11.5 GHz with local oscillator (LO) power of 0 dBm. With an RF input at 5.2 GHz and LO frequency of 5.1 GHz, the simulated downconversion gain versus LO power indicates peak gain of 7.26 dB at LO power levels between 0 and +4 dBm (Fig. 5). The value of 0 dBm was chosen for LO power where conversion gain of 7.176 dB was obtained for the tradeoff between LO power and conversion gain—of particular significance to this low-power design.

Design A Low-Voltage UWB CMOS Mixer, Fig. 6

Figure 6 illustrates conversion gain over a wide RF input frequency range, with conversion gain of 6.0 to 7.2 dB from 1.5 to 11.5 GHz. Figures 7 and 8 show mixer-noise figure performance. Apart from the IF at 100 MHz, the noise figure versus IF is relatively flat, with less than 1-dB variation from 60 to 500 MHz (Fig. 7). Referring to Fig.8, the simulated single-sideband noise figure ranges from 18.4 to 20.5 dB for an RF range from 1.5 to 11.5 GHz at an IF of 100 MHz. The mixer’s relatively large noise figure is due to use of four tail current sources (M1-M4) at the bottom of mixer.

Design A Low-Voltage UWB CMOS Mixer, Fig. 7

Design A Low-Voltage UWB CMOS Mixer, Fig. 8

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