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Testing satellite navigation receivers usually depends on signal simulation to evaluate a satellite-communications (sitcom) receiver under high-dynamic-range conditions.1-3 A third-order direct-digital synthesizer (DDS) is invaluable for such simulation and testing, and the accumulation clock rate for each of the three DDS stages can either be the same or different. Numerous reports have been based on the use of same-clock conditions for these multiple-stage DDS sources,4-6 with few studies of higher-order, hybrid-clock DDS sources, structured with multiple cascade accumulators with different accumulation clock rates.7

To better understand these hybrid-clock, third-order DDS sources, a simulation model was developed and an output phase expression for the model was derived. By analyzing this model, it will be shown that hybrid and same-clock higher-order DDS sources can be combined and their models unified. Simulation results for the model will show that it can be used for high-precision Doppler simulation, and that the hybrid clock operation can greatly reduce power consumption compared to same-clock higher-order DDS operation. 

The function of a DDS accumulator can be expressed as a simple relationship (Eq. 1), where the output of the DDS accumulator is represented as acc(n), with n as the clock number index, n0 as the clock number when the accumulator resets, x as the initial value, and k as the accumulation step.6 When the DDS accumulator is implemented in a field-programmable gate array (FPGA), the output always lags behind the input by one clock cycle. 

Figure 1 shows a third-order, hybrid-clock DDS model, with three cascaded DDS accumulators. The first-stage accumulator is running at a different accumulation clock rate than the other two accumulators. The three accumulators in this hybrid-clock model are defined as the acceleration DDS accumulator (DDS_A), the velocity DDS accumulator (DDS_V), and the phase DDS accumulator (DDS_R), respectively.

DDS Model Tunes Doppler Simulation, Fig. 1

Parameters k0 through k3 are the initial accumulation parameters of each accumulator stage; parameters θ0 through θ2 are the outputs of each different accumulator stage; N0 is the word length of parameter k0; and c1 through c3 are the bits that must be truncated when adding the accumulator output to the initial accumulator parameter. Parameters clk0 and clk1 are clock signals driving the first and additional accumulator stages, respectively, as represented in Eq. 2.

In Eq. 2, the clock frequency division coefficient, W ≥ 1, is an integer, so that the clock rate clk0 will be at integral multiples of clk1. If clk0 < clk1, the influence of the latter two accumulators on the first-stage accumulator can be converted and equivalent to a DDS model with same-clock accumulators. In the case of W = 1, the DDS model degenerates into the same-clock model presented in ref. 6.

Based on the model of Fig. 1, the output of each accumulator stage is derived when W is an unknown parameter. For DDS_A, when its initial value is k2, the step value is k3, and the number of the accumulated clock is m, so that its corresponding output sequence can be obtained according to Eq. 3.

Similarly, when the initial value for DDS_V is k1, the step is θ2(m - 1), and it is possible to calculate the corresponding output sequence by means of Eq. 4:

For the output sequence of DDS_R, while its initial value is k0, the step is θ1(n - 1), and the number of the accumulation clock is n; its output sequence can be expressed as Eq. 5. But since W is an unknown, the right-hand side of Eq. 5 cannot be directly expanded and summed:

Supposing that Y = [n/W], where the square brackets denote rounding the contained value to an integer, it is then possible to perform the summation of Eq. 6:

Incorporating Eq. 6 into Eq. 5 results in Eq. 7:

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