The Internet of Things (IoT) promises that one day, almost all personal electronic devices will be connected by wireless means and capable of communicating with each other. Of course, before such functionality is readily available, many building-block electronic components will be needed to establish the framework for the IoT. One company that has been active in creating different electronic function blocks for it is NXP Semiconductors, which recently added to its lineup of chip microcontrollers with the SmartMX2-P40 platform. This offering is suitable for large-scale projects in the banking and electronic-Government (eGov) markets, which will also inevitably become large parts of IoT activities.

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The device is part of NXP’s big-picture approach to serving wireless business transactions and IoT services by ensuring electronic security and protection against wireless identity theft. It features a reduced-instruction-set-computing (RISC) MRK3-SC core and meets common criteria EAL5+ level certification via the company’s Integral Security architecture. The chip microcontroller, which has been optimized for mass-market chip-card projects, is part of NXP’s efforts to battle electronic crime (notably, anticipated efforts that may come with the growth of the IoT). The SmartMX2-P40 incorporates dedicated coprocessors for asymmetric RSA/ECC and symmetric DES/AES cryptography, and is equipped with a certified hardware abstraction layer (HAL) and crypto library for fast time-to-market. An ISO/IEC 7816 contact interface ensures that the SmartMX-P40 can be used in existing chip-card infrastructures.

Maintaining Security For The Internet Of ThingsNXP offers that the SmartMX2-P40 provides a highly secure platform dedicated to the needs of contact smart-card projects and their end customers. According to the firm, research firms such as eMarketer project that online shoppers in the United States alone will have spent $262 billion in 2013, with about 16% of that coming from mobile commerce (e.g.,  purchases on smartphones. Obviously, electronic and wireless security are serious concerns and important parts of design efforts for these wireless electronic devices.

NXP also announced that its PN544PC, a derivative of its popular near-field-communication (NFC) radio controller (model PN544), is being integrated into some new computing devices. The PN544, which features a communications distance to 10 cm, is based on an 8-b microprocessor architecture with 5-kb of random-access memory (RAM) and is a versatile component for many financial-functioned NFC card devices. The microcontroller includes a self-test function to verify antenna matching, simplifying integration into wireless devices.

In addition, the PN544PC builds upon Intel’s Fourth Generation Core platform with Intel Identity Protection Technology (Intel IPT) together with the embedded NXP NFC solution will provide a basis for secure and convenient e-commerce transactions. This feature will allow payment by online shoppers using MasterPass, the new digital service from MasterCard, simply by tapping their MasterCard contactless card or NFC-enabled mobile phone against the built-in NFC reader and securely completing the transaction with positive identity authentication via Intel IPT.

The Intel IPT furnishes layers of security and identity authentication in addition to those provided by MasterPass so that NFC-enabled contactless card based transactions are protected by a generous amount of security functions. Such electronic security planning will be an important and necessary part of design for all present and future devices that become part of the IoT, especially those devices that will manage financial transactions. Admittedly, while the wireless connection of electronic devices on the IoT will present additional problems in terms of possible jamming and interference—especially when devices are within range of each other and operating at similar frequencies and bandwidths—these security measures will help to ensure that unwanted theft of identity and electronic financial information is kept to a minimum.

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