Unconventional PLLs Simplify Difficult Designs
Modern communications systems rely heavily on a key building block, the phase-lock loop (PLL). While PLL design has been covered extensively over the years, the four techniques described in this article will likely be unfamiliar to most readers. These methods should prove helpful across a wide range of applications, including both analog/TF and digital-signal-processing (DSP) domains.
Those familiar with PLL design will recognize the classic type-2 fourth-order loop filter shown in Fig. 1. This PLL is fourth-order because the single-ended loop filter has three capacitors (C1, C3, and C5) and the voltage-controlled oscillator (VCO) contributes one additional filter pole.
Focusing first on Fig. 1, the phase detector in this case has two outputs that are often labeled as pulse-up (Pu) and pulse-down (PD) outputs. denoting the phase detector gain by Kd (in V/rad), the Vco tuning sensitivity by Kv ( in rad/s/V), and assuming that the loop filter component values are perfectly symmetric, the open-loop gain transfer function can be written as:
With reasonable choices for the additional pole locations compared to a classical type-2 second-order PLL, it is convenient to adopt the classical definition for damping factor and write eq. 8:
These results are fairly standard, and Bode methods can be used to explore the open-loop gain and phase of Eq. 1 quickly.
For a numerical example, assume that a PLL has the following parameters: a natural frequency, ωn, of 2π (20 kHz) rad/s; a damping factor, ξ, of 0.80; a feedback divider ratio, N, of 100; a phase detector gain, Kd, of 0.525 V/rad; and a VCO tuning sensitivity, Kv, of 2p (100 MHz) rad/s/V. To maintain low phase-detector-referred noise floor while not excessively loading the phase detector outputs, resistors R1 and R2 are set at 510 Ω. The remaining component values can be derived using a simple spreadsheet such as shown in Table 1. The only other design parameters needed are the ratios t2/t5 and t3/ t5. These ratios must be as large as possible to preserve PLL gain and phase margin; they were both set to 10 in this example.
A casual inspection of the computed results shows an immediate issue with the design value for R5: It is only 56 Ω. Many operational amplifiers (opamps) could exhibit their own stability issues if configured for such low high-frequency gain. A second concern is that the VCO's Kv value is fairly high, making circuit layout issues between the opamp output and the VCO critical. Nevertheless, calculation of the closed-loop gain functions (ref. 2), H1 and H2 (Eq. 9):
H1(f) = GOL(f)/OL(f)>(9a)> H2(f) = 1/OL(f)>(9b))
using Eq. 1 can be performed as shown in Fig. 3. With the circuit configuration of Fig. 1 left unchanged, there is little recourse available to address these two very real design issues. Another degree of freedom is needed to improve the design. The previous design example can be markedly improved by appending what appears to be a passive lag-lead network following the opamp circuit of Fig. 2. Although it has the appearance of a passive lag-lead network, it is used to perform an entirely different function.
The best way to understand the role of this additional RC section is to mentally replace capacitor C7 with an ideal battery. When the battery voltage is set to precisely the value needed by the VCO to be on frequency, the output voltage from the opamp will be equal to this same value in steady-state operation, and there will be no DC current flow through R7 and R8.
In this context, it is as if the battery is acting like an ideal coarse tuning voltage for the VCO. Since there is no current flow through R7 and R8, the resistive divide ratio R8/(R7 + R8) can be made as small as desired, thereby reducing the effective VCO tuning sensitivity seen at the opamp output by the same ratio. This ratio provides the extra degree of design freedom needed as mentioned in the previous section.
The voltage transfer function of this passive network between the opamp output and the VCO's tuning port input is given by Eq. 10:
where t6 = R8C7 and t7 = R7C7 + t6. To properly use this network, the pole and zero frequencies in Eq. 10 must be placed well inside the closed-loop bandwidth where they will not affect the stability margins of the PLL. Assuming that these frequencies are much lower than the natural frequency of the PLL, Gpost -> t6/t7 for all frequencies of interest. An example will make this more clear.
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Assume that the 100 MHz/V tuning sensitivity is to be reduced to an effective VCO tuning sensitivity of 5 MHz/V. This will require a resistor ratio R8/( R7 + R8 ) = 1/20. Choosing resistor R8 to be 200 O (as discussed subsequently), R7 = 3.8 kO. To maintain the pole and zero well within the PLL's closed-loop bandwidth, C7 = 1 F is chosen corresponding to a zero-frequency of 796 Hz and a pole-frequency of 39.8 Hz. The gain and phase of this network versus frequency are shown in Fig. 4.
Although the additional RC network substantially increases the gain at low frequencies, the gain margin and phase margin remain nearly the same, provided that the PLL natural frequency and damping factor are kept the same. Letting Kveff represent the effective VCO tuning sensitivity, the design equations for Fig. 2 that must be modified are Eqs. 11 and 12:
Kveff = 8/(R7 + R8)>Kv = (t6/t7)Kv (11)
ωn = dKveff)/(Nt1)>0.5 (12)
Appending Eq. 10 to Eq. 1 produces the open-loop gain function of Eq. 13:
GOL(s) = (ωn/s)2{(1 + st2)/3)(1 +st5)>}6-1)/(s + t7-1)> (13)
The other circuit values can be found by using the spreadsheet shown in Table 1, changing the Kv value from 100 MHz/V to 5 MHz/V. The resulting closed-loop gain functions are almost identical to the original case, whereas the additional open-loop gain at low frequencies is apparent as shown in Fig. 5.
The discussion that follows is better facilitated using the annotated schematic shown in Fig. 6. Compared to the original design given in Table 1, resistors R5 and R6 now have a much more practical value of 1120 O and the main feedback capacitors C3 and C4 have been reduced to 10 nF from 0.2 F.
At first glance, it may appear that the large value for R7 and its related Johnson noise could hamper noise performance due to the VCO's tuning sensitivity of 100 MHz/V. Looking back from the VCO's tuning port to the left, however, the tuning port sees the parallel combination of R7 and R8, which is only 190 O. This modified loop filter configuration frequently makes it easier to handle noise problems rather than making them more difficult.
Referring to Fig. 4, the additional RC network increases the open-loop gain for frequencies less than about 1 kHz up to as much as 26 dB. This can be helpful in thwarting low-frequency power supply noise or excessive close-in 1/f noise in the VCO.
The primary disadvantage of the modified loop filter arrangement is that the transient response for any large frequency step is slowed substantially. If the new PLL output frequency requires a large change in the VCO tuning voltage, the active portion of the loop filter must charge or discharge capacitor C7 through the large resistance R7 + R8. In some situations, particularly tracking-loop situations, this characteristic can actually be used to advantage.
The terminology long-PLL1 normally appears in the context of phase-locked receivers like those used for deep-space communications. A representative example is shown in Fig. 7. The IF bandpass filter and baseband lowpass filter normally have reasonably small bandwidths and together result in appreciable group delay that complicates loop stability. Space receivers must usually accommodate appreciable Doppler rates, thereby leading to an even more difficult compromise between closed-loop bandwidth, acquisition capability, and stability. A simple modification of the classic type-2 lag-lead loop filter equations can be used to solve this otherwise difficult design problem.
The open-loop gain (GOL) function for a classic type-2 PLL is given by Eq. 14:
GOL(s) = (Kd/N)2)/(st1)>(Kv/s) (14)
It is a simple matter to rewrite Eq. 14 as Eq. 15:
GOL (s) = ((Kd/N)1) + (t2/t1)>(Kv/s) (15)
where the proportional and integral terms in the active lag-lead network have been separated. Frequency-domain analysis can be used to show that most of the stability issues come from appreciable delay applied to the proportional gain term, whereas the integral term is far more tolerant to delay. The design improvement in the context of Fig. 7 then comes by putting most (if not all) of the proportional gain in loop filter 1 where no group-delay contribution from the narrow bandpass filter comes into play. The remainder of the open-loop gain function (Eq. 15) is incorporated into loop filter 2.
In order to quantitatively look at this design modification further, assume that the group delay through the bandpass filter is represented by tBPF, and the group delay through the lowpass filter is represented by tLPF. Only one of the several possible gain distribution variations will be considered here, where the loop filter transfer functions are given by:
G1(s) = a(t2/t1) (16a) G2(s) = (1 a)(t2/t1) + 1/(st1) (16b)
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where a is an arbitrary gain-term ( 0 a 1 ) that distributes the proportional gain between the two loop filters. Assuming that both VCOs have the same tuning sensitivity and that N = 1, the Laplace transfer function between the phase at the receiver's input, θin, and the phase error seen by the phase detector, θe, is given by Eq. 17:
θe/θin = s2exp(-stBPF)/(s2 + ωn2exp(- stLPF){at2s + 2s>exp(-stBPF)}) (17)
In this form, it is easy to recognize that the effective open-loop gain function is given by Eq. 18:
GOL(s) = (ωn/s)2 exp(-stLPF){at2s + 2s>exp(-stBPF)} (18)
The closed-loop gain function H1 using Eqs. 9 and 18 is shown for a variety of a values in Fig. 8, illustrating how effective this technique can be for constraining what would otherwise be unacceptable gain-peaking. Without this technique, nearly 15 dB gain-peaking would occur as shown; with it, the peaking is reduced to a very acceptable 4 dB. The phase margin versus a for this example is shown in Fig. 9. Evidence of poor long-loop stability in the time domain is manifested as increasingly under-damped phase error transient responses, as shown in Fig. 10 for several values of a. As simple as splitting the lag-lead transfer function apart in Eq. 15 is, this is a very effective way to counter filter-related group delay in a long PLL.
The Haggai constant-phase-margin PLL is named in honor of Ted Haggai, who was a senior scientist at Hughes Aircraft Company some years ago. This technique was mentioned in my 1994 textbook on frequency synthesizers and expanded on further in my 2008 textbook on advanced phase-lock techniques. The method has its roots in the constant phase network methods of Bode nearly 100 years ago. The Haggai PLL uses a modified lag-lead network like the one shown in Fig. 11. The beauty of this method is that the closedloop bandwidth can be varied by a factor of even 100:1 while the phase margin remains nearly unchanged.
In a phase-locked receiver, the phase detector gain is always a function of the input signal to noise ratio (SNR) due to small-signal suppression effects imposed by the noise. Since the PLL's natural frequency is a function of the phase detector gain as shown by Eq. 7, and the PLL's damping factor is a function of natural frequency ωn based upon Eq. 8, the PLL's phase margin normally deteriorates as the input SNR decreases. The PLL's ability to track Doppler frequency error is also degraded under these conditions.
Haggai was granted a patent (US Patent No. 3,551,829, December 1970) on his constant phase margin technique because his method ingeniously solved these problems. The Haggai method is also very useful when the closed-loop bandwidth is to be purposely adjustable over a wide frequency range in a synthesis application. Even though the bandwidth can be changed significantly, the phase margin remains almost constant.
There is no closed-form solution for the lag-lead zeros used in the Fig. 11 schematic diagram. These parameters must be found using numerical methods as discussed in Chap. 6 of ref. 2. In the Haggai loop-filter case utilizing two sections as shown in Fig. 12, its open-loop gain function is given by Eq. 19:
GOL(s) = (ωn/s)21)(1 + st2)/(1 + stF)>x)> (19)
where ( 1 + stx )1
represents the additional lowpass filter section following the Haggai lag-lead network and:
ωn = {KdKv/1 + C2)>}0.5 (20) tF = 1C2/(C1 + C2)>(R1 + R2) (21)
In the case of a step-frequency change applied to the PLL (represented by a stepchange in the VCO tuning voltage of dV), the Laplace transform of the PLL's output phase error is given by Eq. 22:
θ o(s) = dVKv{(1 + stF)(1 + stx)/2(1 + stF)(1 + stx) + ωn2(1 + st1)(1 + st2)>} (22)
A simple design example helps to illustrate how this PLL configuration performs. Based upon design information provided in ref. 2, consider the case where R1 = 1 kO, R2 = 692.928 O, Rx = 1 kO, C1 = 46.78 nF, C2 = 3.436 nF, Cx= 265 pF, Kd = 0.001/p (A/rad), Kv = 2p 25 MHz/V, and N = 1000. The natural frequency given by Eq. 20 is 5.022 kHz. The open-loop gain and phase for this example are shown in Fig. 13. Since the open-loop phase remains almost constant over the frequency range of about 8 kHz to over 200 kHz, the closedloop bandwidth can be varied over this same span with almost no effect on the PLL stability margins. The closed-loop gain functions are very well behaved, as shown in Fig. 14.
There is only one characteristic of the Haggai method that may present an issue, and that is its time-domain transient response behavior. The penalty for bandwidth flexibility with constant phase margin is an extended time domain response tail (as shown in Fig. 15), compared to an optimized traditional type-2 PLL having the same bandwidth. The PLL bandwidth (ωn) is changed over a 10:1 range in Fig. 15, and no hint of loop instability emerges due to the constant phase margin delivered by this method.
The rapid evolution of wireless systems over the past 20 years has led to truly exceptional integrated PLL devices, notably the Platinum family from National Semiconductor and, more recently, the HMC700 PLLs from Hittite Microwave. Even so, if the ultimate in phase noise performance is needed, a mixerbased phase detector of some kind must normally be used. Harmonic-sampling phase detectors are also a member of this category. One major disadvantage that must be addressed with mixer-based PLL approaches, however, is the dramatically reduced capture range that normally results. PLLs that implement the phase detector function digitally usually include a frequency discrimination capability that allows them to achieve phase-lock even if very large initial frequency errors are present, whereas this feature is absent in mixer-based PLLs.
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The quadri-correlator method has been known for a long time, having appeared in Gardner's classic book on PLLs.3 This method, as well as several other related frequency discriminator methods, can be derived from the classic paper by Natali.4 A variant of this method was used in ref. 5 for differentiating between upper and lower sideband mixing products in an offset-PLL. Whereas many methods have been proposed and used to address this frequency pull-in limitation, the quadricorrelator method is particularly advantageous.
The quadri-correlator method gets its name from the fact that it requires inphase (I) and quadrature (Q) components of the RF signal to be resolved. Since the associated phase of the signal is given by Eq. 23:
θ = tan-1(Q/I) (23)
implicit differentiation of this equation, combined with recognizing dθ/dt as radian frequency ω, allows the instantaneous frequency error to be expressed as follows in Eq. 24:
where the overhead dots denote differentiation with respect to time. This result can be closely approximated with several remarkably simple analog circuits to produce a very effective frequency-discrimination capability.
A convenient approximation for the time derivatives in Eq. 24 is Eq. 25:
dI/dt /t (25a) dQ/dt/t (25b)
where t is a small time delay compared to the possible frequency errors involved, and substitution into Eq. 24 thereby produces Eq. 26.
Normally, 1/t is simply lumped in with other gain factors as a single proportionality constant, and the time delays in Eq. 26 can be approximated by simple RC sections, as shown in Fig. 16. The frequency discriminator portion of Fig. 16 can be analyzed using Laplace transforms based upon the simplified model in Fig. 17. The key parameters are tFD, the time delay associated with frequency discriminator; KFM, the gain of the frequency discriminator (in V/Hz); HLPF, the second-order passive lowpass filter that follows the discriminator; and Kv, the VCO tuning sensitivity (in rad/s/V).
The voltage transfer function of the lowpass filter immediately following the frequency discriminator can be simplified, if R5 = R6 = R7 = R and C5 = C6 = C, to the relationship shown in Eq. 27:
HLPF = ωLPF2/(s2 + 4ωLPFs + 3ωLPF2) (27)
where ωLPF = (RC)-1. The bandwidth of the LPF-I and LPF-Q lowpass filters is usually very large compared to the closed-loop bandwidth, so these filters are ignored in Fig. 17 except for the delay that they present as tFD.
From Fig. 17, the open-loop gain can then be written as Eq. 28.
A first-order design equation can be obtained by approximating exp(stFD) as 1 stFD in Eq. 27 as Eq. 29:
HLPF(s) (1/3) (29)
where ? = 4/(3?LPF). The characteristic equation for the system follows as Eq. 30:
with K' = KFMKv/(6pt1). Based on this result, the natural frequency and damping factor for the frequency-locked loop are approximated by Eqs. 31 and 32:
It is immediately clear from these results that γ > K't2tFD is required in order to have any measure of loop stability. It can also be shown that the transient response of the FLL is optimized by choosing to set t2 = tFD.
It is convenient to use Eq. 9 in the content of Eq. 28 for computing the transient response of the FLL to a step change in input frequency. Because of the delay term in Eq. 28, the inverse Laplace calculation must be performed numerically. The example that follows illustrates how effective the quadri-correlator can be for reducing the initial frequency error in an FLL/PLL system such as that of Fig. 16. Parameter details are provided in Table 2. The closed-loop gain functions for this example are shown in Fig. 18 and the well-behaved transient response to a step change in frequency is shown in Fig. 19.
A number of design parameters must be considered when designing an FLL, including the magnitude of the initial frequency error possible, the switching-time required, and the manner in which the FLL is to be transitioned into a PLL configuration once the frequency error has been adequately reduced.
Digital variants of the quadri-correlated design based on Eq. 26 can also be implemented for digital-signal-processing (DSP) applications. Equations 31 and 32 are convenient approximations that can be used to start the design process, while more exact calculations based on Eq. 28 or SPICE simulations can be used to complete a detailed design.
In summary, four unconventional PLL methods have been presented that should strengthen and widen the tools available for different PLL designs. While these four PLL design approaches may be somewhat unfamiliar to many readers, they can help overcome some of the deficiencies of traditional PLL design techniques, such as inadequate open-loop gain at lower loop frequencies. Additional information, including the MATLAB scripts used to create the examples shown here, can be found at www.am1.us/mw_may2011.
References
1. J. P. McGeehan and J. P. H. Sladen, "Elimination of False-Locking in Long Loop Phase-Locked Receivers," IEEE Transactions on Communications, October 1982.
2. J. A. Crawford, Advanced Phase-Lock Techniques, Artech House, Norwood, MA, 2008.
3. F. M. Gardner, Phaselock Techniques, 2nd ed., Wiley, New York, 1979.
4. F. D. Natali, "AFC Tracking Algorithms," IEEE Trans. Communications, Aug. 1984.
5. J. A. Crawford, Frequency Synthesizer Design Handbook, Artech House, Norwood, MA, 1994.