Chip-Scale Atomic Clock Mounts on a PCB, Delivers Greatly Enhanced Performance

This article appeared in Electronic Design and has been published here with permission.

What you’ll learn:

• The performance provided by a next-generation chip-scale atomic clock (CSAC).
• The major functional blocks of the CSAC and how it operates.
• The developer’s support kit and associated user’s guide to facilitate design-in efforts.

If your mental “picture” of an atomic clock is a room-sized unit with all sorts of optical, cryogenic, and electronic systems and associated interconnections (Fig. 1), or even a much-smaller 19-in. rack-mounted unit, that’s not necessarily the reality—if you can accept performance which is less than that available via NIST- or instrumentation-rated systems. In 2011, Symmetricom introduced its SA45 chip-scale atomic clock (CSAC) based on cesium-clock technology (Symmetricom was acquired by Microsemi in Oct 2013; in turn, Microsemi was acquired by Microchip Technology in 2018). It featured accuracy that was two orders of magnitude better than oven-controlled crystal oscillators (OCXOs), and up to four orders of magnitude better than temperature-controlled crystal oscillators (TCXOs).

The latest CSAC from Microchip Technology, the SA65, greatly improves on the performance of that predecessor and is form-, fit- and function-compatible with the SA45 for ease of upgrade and design-in. While the SA65 doesn’t match the performance of the cesium-based clocks at NIST, or even a large rack-mounted unit, it obviously meets significantly reduced size, weight, and power needs compared to those primary and secondary standards.

The module measures just 1.6 × 1.39 × 0.45 inches (approximately 40 × 35 × 11.5 mm), weighs 1.25 ounces (35 grams), and requires under 120 mW of power (Fig. 2). For users who are concerned that this is a radically new technology and thus may be hampered by potential production startup issues, Microchip notes that it has already shipped 138,000 CSAC-family devices.

Applications are primarily centered on mil/aero requirements, including higher-performance GPS receivers, backpack radios, anti-IED jamming systems, autonomous sensor networks, unmanned vehicles, and underwater sensor systems. Essentially, it’s suited for situations where better timing improves performance, or where Global Navigation Satellite Systems (GNSS) time signals are physically unavailable, degraded, limited (fewer than four satellites), or completely denied.

The SA65 CSAC provides RF and 1 pulse per second (PPS) outputs at standard CMOS levels. Short-term stability (Allan deviation or variance; see References 1 and 2) is 3.0 × 10^–10 over a one-second interval (tau or τ), typical long-term aging is <9 × 10^–10/month, and maximum frequency change reaches ±3 × 10^–10 over the operating temperature range of –40 to +80°C. It also accepts a 1 PPS input that can be used to synchro­nize the unit’s 1 PPS output to an external reference clock with ±100-ns accuracy, as well as to “discipline” its phase and frequency to within 1 ns and 1.0 × 10^–12, respectively.

Not only do users want the precision timing from the device, they need to be able to “talk” to it. Comprehensive control, monitoring, and calibration of the SA65 is accomplished via a standard CMOS-level RS-232 serial interface built into unit. The interface is also used to set and read the CSAC’s internal time-of-day clock.

How does the chip-scale SA65 emulate what a larger system does in such a tiny module (although with admittedly lower timing performance as compared to those larger systems)? It’s obviously complicated and requires deep atomic-level physics. In brief, the CSAC is a passive atomic clock, incorporating the interrogation technique of coherent population trapping (CPT) and operating on the D1 optical resonance of atomic cesium.

The key components of the CSAC are a microwave synthesizer, microprocessor, and TCXO (Fig. 3). The microwave synthesizer generates a 4596.3-GHz signal with tuning resolution of approximately 1 × 10^–12. The microprocessor provides multiple functions, including implementation of the frequency-lock loop filter for the TCXO, optimization of physics-package operation, state-of-health monitoring, and command and control through the serial communications port.

In normal operation, the frequency of the TXCO is continuously compared and corrected to the ground-state hyperfine frequency of the cesium atoms contained within the physics package. This improves the stability and environmental sensitivity of the TCXO by four to five orders of magnitude. Of course, such a technology doesn’t come cheap—it’s priced at about $5,500 in single-unit orders and half that amount in lots of 250 or more.

The SA65 datasheet provides the additional specifications, which are needed to more fully characterize a high-performance timing source such as this one. There’s also comprehensive support collateral, including a Developer’s Kit ($1,000) and associated software (Fig. 4), a 51-page User’s Guide, and more.

An academic paper is available for those who want the additional insight on the advanced principles and physical implementation of CSAC devices from a physics perspective (see Reference 3) as well as a broader overview (Reference 4). 

References

1. NIST, “Analysis of Time Domain Data” (Allan Deviation).

2. Wikipedia, “Allan variance.”

3. Lutwak, et al; 36^th Annual Precise Time and Time Interval (PTTI) Meeting, “The Chip-Scale Atomic Clock – Low-Power Physics Package” (2004).

4. Robert Lutwak (Microchip Technology), “Tactical Atomic Clocks” (2019).