Agile ADCs Enable Digital Cellular Receivers
Digital receivers for cellular communications systems require the highest performance levels from analog-to-digital converters (ADCs) and their supporting cast of RF components. The signal chain must be sensitive enough to capture low-level signals, while providing enough dynamic range to handle high-level interfering signals (blockers). Fortunately, the MAX1418 15-b, 65-MSamples/s ADC or MAX1211 12-b 65-MSamples/s ADC from Maxim Integrated Products (Sunnyvale, CA) in combination with the company's 2-GHz MAX9993 or 900-MHz MAX9982 integrated mixers provide exceptional dynamic range for two of the most critical stages in a receiver. In addition, the firm's MAX2027 and the MAX2055 intermediate-frequency (IF) digital variable-gain amplifiers (DVGAs) provide high third-order output intercept (OIP3) performance with the required gain adjustment range for many applications.
For the subsampling receiver architecture shown in Fig. 1, stringent noise and distortion requirements are placed on the ADC. In receiver applications, the lower level desired signal is digitized alone or in the presence of an unwanted signal(s) that can be significantly larger in amplitude. To properly design the receiver, the ADC effective noise figure must be determined under these two signal extremes. The converter's noise figure is determined by comparing its total noise power to the thermal noise floor. For small analog input signals, the thermal + quantization noise power dominate the ADC's noise floor, which is used to approximate the ADC's effective noise figure (NF).
In practice, once the ADC's effective NF is known under small-signal conditions, and the cascaded NF of the analog (RF and IF) circuitry is determined, the minimum power gain ahead of the ADC is selected to meet the required receiver NF. The amount of power gain places an upper limit on the maximum blocker, or highest interference level the receiver can tolerate before the ADC overloads. For BTS applications, the ADC often does not have sufficient dynamic range to meet both the NF requirements (receiver sensitivity) and maximum blocker requirements without implementing automatic gain control (AGC). The AGC can be included either in the RF stages, IF stages, or both.
Other converters in the MAX1418 family are optimized for baseband performance where the input frequency (fINPUT) is less than one-half the clock frequency (fCLOCK/2}. Operating in this frequency range and using these baseband-optimized parts provide the best possible converter dynamic range. These converters include the MAX1419, which is optimized for a sampling rate of 65 MSamples/s, and the MAX1427, which is optimized for a sampling rate of 80 MSamples/s, both with spurious-free-dynamic-range (SFDR) performance equal to −94.5 dBc at baseband.
As an example, the MAX1418 was used as the converter in a front-end signal chain (using specifications listed in Table 1). The MAX1418 can be used with a 14-b interface by not connecting the least-significant bit (LSB). If so used, there is a slight signal-to-noise-ratio (SNR) performance penalty and the SFDR performance remains essentially unaffected. Figure 2 shows the ADC noise contribution in the absence of a large-level blocker. Assume all the analog circuitry in front of the ADC has a cascaded noise figure of 3.5 dB. As a first approximation, suppose a designer's goal is for the ADC to degrade the overall receiver NF by no more than 0.2 dB to meet some target sensitivity in a code-division-multiple-access (CDMA) base-station receiver. This NF value should provide sufficient margin to the air-interface requirements, which is also dependent on the final detector's bit-energy-to-noise-power-spectral-density-ratio (Eb/No) requirement. If the MAX1418 thermal + quantization noise floor value from Table 1 is used, an equivalent NF of 26.9 dB can be calculated when the device is clocked at 61.44 MSamples/s (a 50× chip rate). The ADC noise in the 1.23-MHz CDMA channel bandwidth is 14 dB lower than the noise in the Nyquist bandwidth due to the processing gain achieved. An overall gain of 36 dB is needed to achieve the desired cascaded receiver noise figure value of 3.7 dB.
With 36-dB gain ahead of the ADC, a maximum single tone blocker level above −30dBm at the antenna terminal will exceed the ADC full-scale input. The cdma2000 cellular base-station standard specifies a maximum allowable blocker level of −30 dBm at the antenna terminal. For this example, a 6-dB gain reduction was used to increase the largest allowable blocker signal applied to the ADC providing margin to the standard's specification. Assuming allowable headroom of 2 dB, a 6-dB gain reduction results in a maximum blocker level of −26 dBm at the antenna and +4 dBm at the ADC input (Fig. 3). The cellular standards allow 3-dB degradation in overall (noise + distortion) relative to reference sensitivity when a single-tone blocker is present. The allocation of individual noise and distortion components is left to the designer.
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Suppose the designer allows the RF front-end cascaded noise plus distortion to degrade the NF by 1 dB (from the nominal 3.5 dB) when the blocker is present with 6 dB of AGC applied. With only 30 dB of gain in front of the ADC and an effective NF of 29.4 dB determined by the ADC SNR performance, the cascaded receiver NF is 5.7 dB in the "blocked condition," which is a 2-dB degradation from the 3.7-dB NF calculated for receiver sensitivity. Because this calculation does not take into account the spurious performance, an additional 1-dB degradation can be allowed for the ADC's SFDR performance. Instead of calculating noise and SFDR contributions separately, the signal-to-noise-and distortion (SINAD) figure of merit could have been used to compute the effective NF when a blocker signal is present.
The subsampling architecture can be used with a single downconversion architecture if sufficient SNR and SFDR performance can be obtained from the converter at higher IFs. Maxim's MAX1211 is a 12-b 65 MSamples/s converter (Table 2) also shows the performance of an improved version, available in about one month) designed with this architecture in mind along with pin-compatible 80- and 95-MSamples/s versions that will soon be released. The family of converters allows direct-IF sampling for input signals to 400 MHz along with advanced features such as differential or single-ended clock input, clock duty cycles from 20 to 80 percent, data valid indicator allowing the simplification of clock and data timing, 2's complement or gray code digital output data format, and a compact 40-pin thin QFN package (6 × 6 × 0.8 mm).
Single-conversion architectures offer significant advantages compared to double-downconversion (DDC) receivers. For example, by eliminating the second downconversion mixer, second-IF gain stages, and second LO synthesizer circuitry, the parts count and board space can be reduced by approximately 10 percent and cost by $10 to $20. Frequency planning is also simpler. A cdma2000 personal-communications-services (PCS) receiver, for example, might have a first IF centered in the sixth Nyquist band at 169 MHz and bandwidth of approximately 1.24 MHz for a sample rate of 61.44 MSamples/s and synthesizer reference frequency of 30.72 MHz. With the same first IF, a DDC architecture assumes a second IF centered in the second Nyquist band at 46.08 MHz.
Spurious search assumptions for both architectures (for an RF carrier near the upper end of the PCS band) are listed in Table 3. The simpler architecture yielded 134 total spurious signals in the RF receive band, receive image band, IF band, and IF image band, mostly higher-order products that will not degrade receiver performance. The DDC approach yielded over 2400 spurious products, in the RF and both IF bands. Although many of these products can be reduced by careful PCB layout and filtering, a significant number of lower-order spurious signals will be difficult to minimize.
Before an ADC can convert received signals to the digital realm, those signals must be translated down in frequency through a mixer. By their nonlinear nature, mixers produce undesired spurious signal products according to the well-known relationship
fIF = ±mfRF ±nfLO
where:
fIF, fRF, and fLO refer to the frequencies of the signals at the mixer's IF, RF, and LO ports, respectively, and m and n are integer harmonics of both the RF and LO frequencies that mix to create numerous combinations of spurious products.
Traditional passive mixers employ diodes to achieve the signal mixing effects. More recently, however, integrated active mixers, such as the balanced models MAX9993 and MAX9982, are becoming more popular. Balanced mixers reject certain spurious responses when m or n is even resulting in excellent second-order harmonic performance. Ideal double-balanced mixers reject all responses where m or n (or both) is even. In all double-balanced mixers, the IF, RF, and LO ports are mutually isolated. With properly designed baluns, such mixers can have overlapping RF, IF, and LO bands. LO noise in a mixer reciprocally mixes with high-level input blocking signals to desensitize a receiver.
In addition to providing gain (rather than the loss of a passive mixer), the MAX9993 and MAX9982 mixers have integrated RF baluns on the RF and LO ports and built-in low-noise LO buffers that result in minimal receiver desensitization when blockers are present. For example, if an LO driving the MAX9993 has a sideband noise performance of −145 dBc/Hz, the typical LO noise for the mixer is −164 dBc/Hz. As a result, the composite sideband noise performance is degraded by only 0.05 dBc/Hz to −144.95 dBc/Hz.
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A particularly troublesome second-order mixer spurious response is the half-IF response which occurs when m = 2 and n = −2 for low-side rejection and when m = −2 and n = 2 for high-side rejection. Following the 169-MHz IF example, if the desired RF signal is 1909 MHz (Fig. 4), the corresponding LO signal is 1740 MHz. Though the CDMA RF and IF carrier occupies a 1.24-MHz bandwidth, it's illustrated as a single frequency indicating the center carrier frequency. An undesired RF signal at 1824.5 MHz will cause a half-IF spurious product at 169 MHz:
2fHalf-IF − 2fLO
= 2(fRF − fIF/2) − 2(fRF − fIF)
= 2fRF − 2fIF/2 − 2fRF + 2fIF = fIF
which results in 2(1824.5 MHz) − 2(1740 MHz) = 169 MHz. The amount of rejection, called the 2 × 2 spurious response, can be predicted from the mixer's second-order intercept point (IP2). The 2 × 2 IMR or spurious values in Fig. 5 are taken from the data sheet for the MAX9993 mixer. The signal levels are referred to the input of the mixer for which the input IP2 (IIP2) performance is calculated:
IIP2 = 2IMR + PSPUR = IMR + PRF
= 2(+70 dBc) + (−75 dBm) = +70 dBc + (−5 dBm) = +65 dBm
Image-reject filters used in the RF path immediately ahead of the mixer attenuate any amplifier harmonics. The noise filter in the LO path attenuates harmonics caused by the LO injection source. High-level input signals create distortion or intermodulation products and can be quantified by calculating the intercept point, either at the input or output of the device or system (the output intercept point is merely the input intercept point plus the gain (in dB) of the device or circuit under test). For the case where the mixer LO power is held constant, the order of the intercept point or distortion product is determined only by the RF multiplier and not by the LO multiplier since only variations in the RF signal are of concern. The order refers to how fast the amplitudes of the distortion products increase with a rise in input level.
The high-speed ADCs are well suited for designing digital cellular receivers with low noise and wide dynamic range and, with the firm's active mixers, form a simple high-performance single-conversion receiver. The addition of the company's DVGAs provide typical OIP3 performance of +40 dBm over a wide gain-adjustment range, to complement the ADC performance. For more information on any of these components, visit the company's website. Maxim Integrated Products, Inc., 120 San Gabriel Dr., Sunnyvale, CA 94086; (408) 737-7600, FAX: (408) 737-7194, Internet: www.maxim-ic.com.
REFERENCES
- Relevant application notes can be found on the website at www.maxim-ic.com, including AN 728, "Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1," AN 729 "Dynamic Testing of High-Speed ADCs, Part 2," AN 1197 "How Quantization and Thermal Noise Determine an ADC's Effective Noise Figure," AN 1929 "Understanding ADC Noise for Small and Large Signal Inputs for Receiver Applications," AN 1838 "Mixer 2x2 Spurious Response and IP2 Relationship," AN 2021 "Specifications and Measurement of Local Oscillator Noise in Integrated Circuit Base Station Mixers," and AN 2371 "Consider Overall Cascaded Performance When Comparing Integrated RF Frequency Mixers to Passive Mixer Solutions."
- James Tsui, Digital Techniques for Wideband Receivers, Artech House, Norwood, MA, 1995.
- Peter Vizmuller, RF Design Guide, Systems, Circuits, and Equations, Artech House, Norwood, MA, 1995.
- Jhong Sam Lee and Leonard E. Miller, CDMA Systems Engineering Handbook, Artech House, Norwood, MA, 1998.