Peregrine Unveils New Quarter-Micron Foundry Process

Aug. 31, 2004

Silicon-on-insulator semiconductor technology offers distinct advantages in integration, isolation, and power consumption compared to more conventional semiconductor processes, and one of the industry's leading suppliers of this technology has just improved its offerings. Peregrine Semiconductor Corp. (San Diego, CA) has just announced the availability of its new quarter-micron UltraCMOS silicon-on-sapphire process technology for foundry services. The versions of the new technology, the GA and GC processes, complement the company's existing half-micron FA and FC processes, and will push transistor performance to maximum cutoff frequencies exceeding 100 GHz. The initial quarter-micron foundry offerings will be available on a quarterly basis beginning with the fourth quarter of 2004 through multiproject runs, which allow customers to fabricate their designs as a designated part of a wafer. Peregrine's foundry engineering group provides all necessary design support, including a Cadence-based front-end-to-back-end process design kit (PDK). Customers can purchase a wafer tile area of 3 mm square on a shared mask set and receive a minimum of 50 semiconductor dice.

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About the Author

Jack Browne | Technical Contributor

Jack Browne, Technical Contributor, has worked in technical publishing for over 30 years. He managed the content and production of three technical journals while at the American Institute of Physics, including Medical Physics and the Journal of Vacuum Science & Technology. He has been a Publisher and Editor for Penton Media, started the firm’s Wireless Symposium & Exhibition trade show in 1993, and currently serves as Technical Contributor for that company's Microwaves & RF magazine. Browne, who holds a BS in Mathematics from City College of New York and BA degrees in English and Philosophy from Fordham University, is a member of the IEEE.