Next, an updated schematic was created that incorporated the microstrip lengths and widths. The schematic contains both MTEEX$ and MTRACE2 elements. The MTEEX$ is a microstrip tee-junction element, and the MTRACE2 element is a microstrip meander line element. The MTRACE2 elements are employed so that the quarter-wavelength microstrip lines can be bent in the layout environment.
The last step involved creating the physical board layout, with a goal of minimizing the board area without compromising performance. The application brief explains how to add bends to microstrip lines in the layout. The document also discusses how to account for coupling between sections by utilizing automated-circuit-extraction (ACE) technology. ACE is a tool that can extract high-frequency models of the layout—including coupling effects.
After completing the layout, the next step was to further miniaturize the layout. The AXIEM 3D planar electromagnetic (EM) simulator was used for final EM verification.
National Instruments Corp., 11500 N Mopac Expwy., Austin, TX 78759-3504; (877) 388-1952; www.awrcorp.com.