The Global Positioning System (GPS) has evolved in both its specification and the capabilities delivered by its satellites. Similarly, the equipment that uses the precise output data from those satellites has grown in quantity, variety, and its ability to support key infrastructure elements and higher performance demands. In a 10-page white paper titled, "Design Considerations for Optimizing Stability in GPS Disciplined Frequency Standards," Precise Time and Frequency, Inc. details the design of the phase-locked loop (PLL) in particular.
The paper begins with a system overview, noting that GPS architectures comprise simply a GPS receiver "engine," a high-performance oscillator, and the electronics needed to implement a PLL. If it is designed correctly, that PLL will not simply phase-lock the oscillator to the GPS-engine output. It also will extract the last bit of performance from satellite signals while delivering optimal performance to
end-user applications.
The design and performance of a 1-pps PLL for a GPS frequency standard is provided. It utilizes a high-quality, ovenized voltage-controlled crystal oscillator (OVCXO). Equations are provided for differences, the loop compensation transfer function, transfer function in the frequency domain, and more. The paper finds that the use of an ovenized VCXO provides good stability to roughly 100 s, which requires a slow loop with a time constant of about 100 s.
Design tips also are provided for the lowpass filter. To preserve stability, for example, the pole of the lowpass filter must be at least a decade higher in frequency than the loop bandwidth. The paper cautions that higher bandwidths will result in increased short-term noise from the GPS engine. A table is provided to illustrate this point. The document closes with a discussion of acquisition versus locked modes.
Precise Time and Frequency, Inc., 50L Audubon Rd.,
Wakefield, MA 01880; (781) 245-9090, FAX: (781) 245-9099, www.ptfinc.com.
