Enabling Next-Gen Intelligent Wearables with Low-Power Memory
This video appeared in Electronic Design and has been published here with permission.
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Low-voltage design methodologies are becoming more prevalent as a route to cutting operating power. This is achieved by dynamically reducing operating voltages in line with the application's processing demands. In some designs, power demands of the memory can account for 50% of the total device power budget. For battery-powered applications with a constrained form factor, this creates huge challenges.
Standard logic cells can, with careful design, operate over a wide voltage range, often close to near threshold voltages. However, off-the-shelf SRAM IP can only operate around the process's nominal voltage.
EverOn SRAM IP is specially designed for these kinds of systems, where the voltage is adjusted to save power with operation from the process nominal operating voltage all the way down to the bit-cell retention voltage that effectively dictates the lowest possible operating voltage. In a leading 40-nm process technology, this means from 1.21 V down to 0.6 V without any additional circuitry or power rails. Hence, the voltage of the chip can be dynamically adjusted up and down in tandem with the performance requirements.
We talk to Paul Wells, CEO of sureCore, about how the company's SRAM IP enables customers to minimize power demand increases and gain fast time to market.
