Design A B3G Receiver Front End
Markets for mobile communications appear to be poised for growth, given the desire of wireless network customers for increased voice, data, and video services. Current third-generation (3G) networks offer considerably more capability than earlier second-generation (2G) systems, but problems arise when newer equipment is not compatible with earlier standards. These problems will only be compounded by the installation and emergence of fourth-generation (4G) networks and handsets. But a solution may be available in the form of "beyond-thirdgeneration" (B3G) wireless networks and handsets.
Compared with 3G mobile communication, 4G systems will undergo a qualitative change in terms of technology and applications, requiring greater efficiency to support higher amounts of traffic at higher data rates. B3G technology, which is often referred to as part of 4G technology, supports wired and wireless access and it is capable of nonsymmetric data transmission at rates exceeding 2 Mb/s. Data rates for 4G wireless networks promise to reach 100 Mb/s for mobile customers and better than 1 Gb/s for fixed use. As customers' requirements move toward the capabilities of 4G systems, interest grows in the capabilities of B3G networks and equipment. At present, regions such as China, Europe, and the United States, as well as companies such as NTT DoCoMo and Samsung, have made significant breakthroughs in researching and field testing B3G systems.
Currently, the multiband orthogonal frequency division multiplexing (MB-OFDM) format proposed by Intel and Texas Instruments divides the ultrawide-bandwidth (UWB) 7.5-GHz spectrum from 3.1 to 10.6 GHz into 128 subbands. Each subband transmits using a bandwidth of 528 MHz, placing great demands on the performance of the RF front end and particular components, such as the low-noise amplifier (LNA) and frequency conversion mixer; limitations in handling such a wide bandwidth are also evident in some of the digital hardware, including the baseband analog-to-digital converter (ADC). To relax the requirements for the hardware, in double-carrier OFDM (DC-OFDM) the bandwidth of each subband is cut in half, reducing the complexity and power consumption. To meet the needs of B3G systems under DC-OFDM requirements, a receiver front end was developed based on a zero-intermediate- frequency (zero-IF) architecture.
One of the keys to the high performance of a B3G system is the RF receiver.1,2 It features zero-IF analog quadrature mixing for small size, low cost, and ease of integration as well as helping to reduce the requirements of the baseband ADC in DC-OFDM systems. To better understand the design of a receiver for a B3G system, a B3G receiver operating from 3.4 to 5.0 GHz will be analyzed (Fig. 1). The receiver includes an LNA, frequency mixer, broadband phase shifter, and other key components. Computer-aidedengineering (CAE) simulations were performed on the core components to ensure optimal performance.
The LNA is a key component in the receiver, since the performance of the receiver is directly affected by its gain, noise figure, linearity, and other parameters.3 In designing an LNA for a B3G receiver, it should provide enough gain to overcome any noise added by components following it in the signal-processing chain, such as the mixer, especially when the available power supply is limited. It should achieve low power consumption, and it should provide low noise figure for maintaining good system dynamic range. The LNA should also provide a good input impedance match to ensure efficient transfer of signal from input to output. Because of tradeoffs involved in many of these parameters, any design process should be based on a balanced approach to optimum performance.
The wideband LNA designed for the B3G receiver employs the input impedance of a cathode-input amplifier to meet requirements for input impedance matching. Output matching circuits used as an output buffer were realized by adopting a source-follower configuration, which has a large input resistance and small output resistance as well as high load capacity. By analyzing the input and output matching circuits by means of CAE simulations, the B3G LNA was designed (Fig. 2). The input achieves broadband impedance matching by means of a common-gate structure with a 3-GHz cutoff frequency. The output matching network has a source-follower configuration to achieve maximum output power.
The LNA employs two cascaded stages to meet the requirements of the B3G receiver. The amplifier simulations are based on the 0.18-μm silicon CMOS process model library from Taiwan Semiconductor Manufacturing Company (TSMC, www.tsmc.com). Simulations were performed using the 2008 version of the Advanced Design System (ADS) CAE simulation software from Agilent Technologies (www.agilent.com). Simulation results for the LNA are shown in Fig. 3.
The LNA's first stage is as a common-gate structure for good input impedance matching for achieving optimum tradeoffs for noise figure, gain, port matching, and linearity. Figure 3 shows that the LNA covers a frequency range of 3 to 5 GHz with measured performance of 19 dB gain, 2 dB noise figure, and third-order intercept point of -1 dBm. It provides good gain and noise flatness, meeting the performance requirements of a B3G receiver system.
In considering the design of the B3G receiver's mixer, the range of the receiver local oscillator (LO) has a significant impact on the conversion gain, linearity, noise figure, and other mixer performance parameters. The switch devices used in the mixer should provide adequate voltage swing for the LO. However, the mixer's switch devices will discharge as a result of the parasitic capacitance of the device common-source node, likely causing a sharp pulse if the voltage swing of the receiver's LO is too large, causing the mixer's switch transistors to push beyond the saturated region and degrade the performance of the mixer.
In general, the voltage swing should be about 100 to 300 mV for an MOS tube switch.4 Another consideration for the LO should be that interference caused by reflected signals must be avoided; thus, the LO should be properly matched to the 50-O characteristic impedance of the system.
A simple resistive-capacitive (RC) matching circuit was applied to the mixer, resulting in nominal gain attenuation only at the lowand high-frequency end of the mixer's frequency range. The proposed LO matching circuitry is suitable for wideband gain of about 0.5 to 0.75 dB over a frequency range of 3.1 to 10.6 GHz, with low attenuation to meet the design requirements. The resistance was set to 50 O to target good impedance matching at the mixer's RF input port. By adopting two LC circuits, it was hoped to match the RF input signal impedance and maintain the return loss of the input signal at a minimum over the frequency range of 3.1 to 10.6 GHz.
One of the concerns in designing a zero-IF receiver is the DC offset component from the mixer. It is caused by 1/f device noise from the mixer switches as well as by the generation of second-order intermodulation components and parasitic capacitances, as learned by an analysis of the mixer and its matching circuits. Therefore, a fixed bias current was added between the mixer switches to reduce effects caused by 1/f noise, and an inductor was added in series with switch transistor to absorb the capacitive charging and discharging currents, and so reducing the interference effects of the mixer's parasitic capacitance.
In the mixer, the RF signal has the highest amplitude, with the greatest tendency to create unwanted interference or spurious products, so mixer linearity is a key performance design goal. As with the LNA, appropriate gain from the mixer can help to suppress noise from the circuits following it. By again using the ADS software to simulate the mixer circuit, assuming TSMC's 0.18-??m CMOS process as the basis for the design, the transmission gain, port isolation, 1-dB compression point and third-order intermodulation point of the mixer were simulated from 3 to 10 GHz.
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Figure 5 shows that the 1-dB compression point occurs at about -15 dBm, with the third-order intermodulation point at around -5 dBm. From 3 to 5 GHz, the gain error is only 1 dB while the input isolation is at least 20 dB. The simulated results meet the performance requirements of the B3G receiver.
One of the limitations of a zero- IF receiver lies in the fact that the in-phase (I) and quadrature (Q) signal paths are not balanced, so that a sharp degradation in system performance takes place when any phase shifting occurs in the LO signal. Generally, quadrature LO signals can be produced by an RC-CR phase-shifting network; the input signals to such a network are phase shifted by 45 deg. The amplitude of the two quadrature output signals (I and Q) is equal only when the frequency is equal to ? = 1/ RC. Unfortunately, a single-stage RCCR phase-shifting network can only achieve a full gain match at one frequency. The phase and gain matching are particularly sensitive to any RC-CR phase-shifting network adaptation.
In order to achieve the quadrature phase shift necessary for the B3G receiver, a broadband phase-shifter module was added to the RF front-end to reduce the sensitivity of the zero-IF receiver to phase deviations. The performance offered by two-stage broadband phase-shifting networks was improved by adopting a three-stage broadband phaseshifting network, as shown in Fig. 6.
The previous two-stage matching network resonates at frequency points, f1 and f2, which are given by f1 = 1/2pR1C1 and f2 = 1/2pR2C2 and determined by adjusting the value of each RC network. By doing so, input signals in the frequency range from f1 to f2 can achieve orthogonal signals with excellent amplitude and phase balance between the signal components.
The maximum gain error occurs in the geometric mean frequency points for the two resonant frequencies. Because of this, an additional stage RC network was added. The third-stage resonant frequency lies to the geometric mean frequency points of the other two resonant stages. Multisim software from National Instruments was used to provide the simulated performance shown in Fig. 7.
Figures 7 and 8 show that output signal maintains good orthogonality with input signals from 1.6 to 6.4 GHz. The signals maintain good in-band phase-frequency characteristics with good orthogonality, with amplitude attenuation of about 5.692 to 5.875 dB. An attenuation error of 0.163 dB does not impact the overall system performance.
As the simulations show, the proposed DC-OFDM biorthogonal zero- IF RF receiver meets the performance requirements of modern communication systems.5,6 Due to the limitations of currently available devices, an experimental verification circuit was created to verify the performance of the proposed circuit compared to a traditional zero-IF receiver.
For comparison, different receiver systems were set with the same phase errors to test receiver sensitivity to phase. An experimental test vector graph was used for comparison.7 The vector and star map of the proposed receiver program are far superior to those for the traditional zero-IF receiver program after simulation and experimental test when there exists phase error in the system. The proposed design provides about 10 to 15 dB greater image rejection than a traditional zero-IF receiver.
The proposed DC-OFDM biorthogonal zero-IF receiver features an analog crossed-field balanced mixer to reduce the requirements of the ADC. The biorthogonal zero-IF receiver format offers a practical solution to the problems of I/Q phase and amplitude balance and DC offset in zero-IF receiver architectures. The proposed receiver shows great promise for B3G and other emerging broadband wireless technologies.
ACKNOWLEDGMENT
This work was supported in part by the National Scientific Foundation of China (No. 60872022), Kechun Tian, Professor, Director of Research, Mobile Communication and Personal Communication.
REFERENCES
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