Put To The Test
Circuit simulations were performed with ADS2009 Advanced Design System (ADS) software from Agilent Technologies, with the circuit model split into a two-level hierarchy (Fig. 4). The upper level consists of blocks representing the MMIC, the signal dividing/combining circuitry, and the impedance-matching functions. Each dual amplifier, Q1 and Q2, is represented by identical two-port S-parameter (.s2p) files. The S-parameters were previously extracted on a test fixture of similar material (10-mil-thick RO4350 circuit-board material) and then applying a through-reflect-line (TRL) calibration to shift the reference planes to the package edges.
With the same test fixture, the device’s noise and linearity parameters were extracted using automated source and load-pull tuners from Focus Microwaves. The ~0.2-dB NFMIN value is particularly challenging to extract because it can be easily obscured by the combined losses of the mechanical tuner and the required APC7-to-3.5-mm coaxial connector adapter. The inductors and hybrid couplers are modeled with their manufacturers’ .s2p data. Other passive components are modeled using their equivalent-circuit models, including their lower-order parasitic values.
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To validate the designed input and output matching networks, the modeled source impedance, ΓS, and load impedance, ΓL were compared with previously measured source- and load-pull contours. The ΓS and ΓL modeled values were obtained via simulation with the ADS “S-parameter probe” component. The balanced LNA MMIC makes it easy to achieve good noise performance because the 0.3-dB constant NF circle is large and even encompasses the chart center (Fig. 5, left). Because of this, the input networks comprising L1 - C3 and L2 - C16 are designed to function as bias tees rather than as impedance/noise matching networks.