Download this article in .PDF format
This file type includes high resolution graphics and schematics when applicable.

Since the United States’ Federal Communications Commission (FCC) earmarked the spectrum from 3.1 to 10.6 GHz for ultrawideband (UWB) communications use, interest has increased in the development of components for this broad bandwidth. The frequency band holds great promise for high-data-rate wireless communications and is geared to co-exist with licensed wireless applications within the more narrowband segments in that frequency range. Of course, producing high-frequency components capable of operating within the UWB frequency range—such as low-noise amplifiers (LNAs)—is critical to the use of practical UWB applications.

Unfortunately, the LNA is one of the greater challenges in terms of UWB components. But with the proper circuit design and semiconductor process, such a broadband low-noise amplifier can be produced with high gain and low noise figure.

Of course, minimizing the power consumption of an LNA for UWB applications is another important requirement. This is no trivial design task, even with the benefit of excellent modern semiconductor processes. UWB LNAs for frequency bands of 3.0 to 5.0 GHz and 3.1 to 10.6 GHz have been widely reported based on silicon CMOS technology.1-6 Another UWB LNA was reported for the frequency band of 2 to 6 GHz, with current reuse topology utilizing a noise-shaping technique.7

The current report highlights a broadband CMOS LNA for UWB applications from 3 to 7 GHz. It employs current-reuse techniques to minimize power consumption and enhance gain at the upper end of the frequency range. A shunt peaking inductor was used to improve flatness gain and to increase the total bandwidth, while a common-drain amplifier helps achieve a wideband output impedance match for measurement purposes.

Current Reuse Gains UWB LNA, Fig. 1

The proposed LNA is a two-stage amplifier with a current-reuse cascade common source structure, useful both for saving power consumption and maintaining good power gain. The two-stage design, initially targeted for power consumption of 6 mW from a +1-VDC supply, is shown in Fig. 1. This results in drain current of approximately 6 mA. Assuming a 6 mA current drawn by transistor M1 for the first stage, the calculated size for transistor M1 is approximately 150 μm based on Eq. 18:

ID ≈ 0.5μnCox(W/L)(VGS1 – Vt)2   (1)

where:

VGS1 = +0.7 VDC;

Vt = +0.5 VDC; and

μnCox = 369 μm for a typical 0.18-μm silicon CMOS semiconductor process.

The required transconductance, gm1, can be determined by Eq. 2:

gm1 = ∂IDD/∂IGS1 = μnCox(W/L) (VGS1 – Vt)   (2)

Rearranging Eq. 1 to:

(VGS1 – Vt = [2IDDnCox(W/L)]0.5

and substituting into Eq. 2, the equation for gm1 can be simplified to Eq. 3:

gm1 = [2μnCox(W/L)ID]0.5 = (2βID)0.5   (3)

where β = μnCox(W/L) is known as the transconductance parameter. Hence, the calculated gm1 is approximately 60.7 mA/V.

By ignoring the Miller effect of gate-drain capacitance (Cgd1) on transistor M1, the input impedance of M1 can be given by Eq. 49:

Zin1 = jω(Lg1 + Ls1) + (1/jωCgs1 + gm1Ls1/Cgs1   (4)

where:

gm1 = the transconductance of M1;   

Cgs1 = the gate-source capacitance of M1;

Ls1 = the source degeneration inductor; and

Lg1 = the gate input inductor.   

The real part of the input impedance in Eq. 4 is given by Eq. 5:

ReZin1 = gm1Ls1/Cgs1   (5)    

With given values of gm1 and Cgs1, the desired impedance match to Rs (usually 50 Ω) can be obtained by setting Ls1 accordingly. The imaginary part of the input impedance can then be compensated with an input matching inductance, Lg1. The corresponding resonant frequency, ω0, is approximated by Eq. 6:

ω0 ≈ [1/(Ls1 + Lg1)Cgs1]0.5   (6)

The source generation inductor, Ls1, is added for linearity and stability improvement, whereas the gate inductor Lg1 is needed for impedance matching between the source impedance and input of transistor M1. In this design, the value of inductor Ls1 is chosen to be small enough (approximately 0.5 nH) so that it could be easily replaced by a bondwire inductance in order to reduce the chip area when necessary. Next, the value of gate inductor Lg1 is calculated from Eq. 6 to be approximately 1.5 nH using a resonant frequency of 5 GHz.

The current-reuse topology employs transistor M2 stacked on top of the input transistor M1 to save power consumption. The current-reuse function is implemented by Ld1, Lg2 and Cg2 to boost gain. Inductor Lg2 must form a series-resonant circuit with capacitance Cg2 and the input capacitance Cgs2 of transistor M2 to create a low-impedance path to couple the output of M1 to the input of M2, while inductor Ld1 is chosen to be large enough to provide a high-impedance path to block the signal in the desired band.10 Parameter Cbp is a bypass capacitor. Therefore, the input can be amplified twice under this concurrent scheme.

It should be noted that the series resonant circuit consisting of Lg2 and Cg2 exhibits a narrowband characteristic. Consequently, the current-reuse function is maximized around the resonant frequency, which is designed to enhance the gain at the upper end of the desired frequency band. 

Download this article in .PDF format
This file type includes high resolution graphics and schematics when applicable.