Improvements in process technologies have made it possible to implement highly integrated, low-cost circuits in silicon CMOS that can work above 20 GHz. With increasing use of K-band frequencies from 20 to 40 GHz for video broadcasting, telephone communications, analog television distribution, and various military applications, silicon CMOS semiconductor processes can provide the active circuits and performance levels needed to support these growing applications.

As the first active function block in a receiver front-end design, a low-noise amplifier (LNA) is a key component in that system. High gain and low noise figure for the LNA are essential for receiving and processing weak incoming signals.1 At present, a large number of silicon CMOS LNAs are designed for use above 20 GHz. For example, a 23-GHz LNA with electrostatic-discharge (ESD) protection, 7.1-dB gain, and 4-dB noise figure has been implemented in a 45-nm planar bulk-CMOS process technology.2

Reference 3 reports of an LNA fabricated with an 0.18-μm CMOS process that is capable of 13.1-dB gain and 3.9-dB noise figure at 24 GHz. A 32-GHz LNA fabricated with a standard 0.18-μm CMOS technology obtains 10.2-dB gain and 4.62-dB noise figure.4 A common-gate LNA implemented in a standard 0.18-μm CMOS process with a capacitor cross-coupling scheme to boost transconductance (gm) operates at 60 GHz.5 

These outstanding silicon CMOS LNAs do not provide a variable-gain (VG) function, however. A variable-gain LNA (VG-LNA) can not only prevent a receiver from entering saturation conditions for relatively large-amplitude input signals, but also can mitigate the linearity requirement of the following mixer and maximize the dynamic range of the overall system.6 A gain-control mechanism is typically needed for many LNA circuits. Recently, a number of VG-LNAs have been developed.1, 6-8 However, they typically suffer from large DC power consumption or low gain, among other limitations plaguing K-band applications.

In an attempt to formulate a solution to these issues, a cascade VG-LNA was designed in a 0.18-μm silicon CMOS process for K-band communications-systems applications. Leveraging a resistance-feedback, current-reuse approach to address noise-figure input matching tradeoffs, the LNA manifests peak gain of 21.1 dB and a noise figure of 3.0 dB at 26 GHz ,with power consumption of only 6.48 mW. It includes a continuous gain-tuning range of 14.5 dB without degrading input and output matching behavior.


Variable-Gain LNA Reaches 26 GHz, Fig. 1

Variable-Gain LNA Reaches 26 GHz, Fig. 2

Figure 1 shows the basic topology of an amplifier with resistive-feedback input stage. The design can be studied with the simplified model depicted in Fig. 2. In addition, gain (A), noise figure (NF), and input impedance (Zin can be calculated using Eqs. 1, 2, and 3, respectively9:

|AV| ≈ gm x (RF x RL)      (1)

NF ≈ 1 + [(2/(3gmRS)] x [(1/RS) + RS/ RF2] + [(2f2gmRS/3f2Tmin + (RS/RF)     (2)

Zin ≈ (RF + RL)/(1 + |AV|)   (3)


gm = the transconductance of transistor M;

RL = the load resistance; and

RF = the feedback resistance.

The circuit is assumed to be connected to a source generator with source impedance, RS, that is typically 50 Ω.

Variable-Gain LNA Reaches 26 GHz, Fig. 3

Resistive feedback can be implemented with a current-reuse technique, as depicted in Fig. 3(a).10 Stacking both NMOS and PMOS transistors, the overall equivalent transconductance is increased from gm to gmN + gmP for the same bias current. Furthermore, removing load resistance RL enables this configuration to maintain the transistors in the saturation region with a minimal supply voltage, and without design tradeoffs.6,9 In the current reuse configuration of Fig. 3(a), Eqs. (1) through (3) are kept the same according to the equivalent values listed in the table.

Variable-Gain LNA Reaches 26 GHz, Table

In the present amplifier design, an NMOS transistor replaces the traditional feedback resistor as shown in Fig. 3(b). In an ideal amplifier, the feedback resistance and gain characteristics are almost equivalent. The resistance value of the NMOS transistor can be derived as6:

rds ≈ L/[KW(Vgs - VT)]            (4)


K = Boltmann’s constant;

W = the effective channel width;

L = the effective channel length; and

VT = the threshold voltage.