To demonstrate the effectiveness of the design approach, a 26-GHz VG-LNA was designed and fabricated using a standard 0.18-μm CMOS process from TSMC. The circuit draws only 6.48 mW from a +1-VDC supply. Results were obtained using the post-layout simulation features of the Advanced Design System simulation software from Agilent Technologies. Figures 6 and 7 show gain and noise figure, respectively, as functions of frequency. The small-signal gain has a peak value of 21.1 dB and the noise figure has a minimum value of 3.0 dB at 26 GHz. Figure 8 shows input and output return losses, with minimum input and output return-loss levels of 23.3 dB and 21.6 dB, respectively.

Variable-Gain LNA Reaches 26 GHz, Fig. 8

As Fig. 4 indicates, controlling the gate voltage VC for device MC in the first stage can provide controllable gain. As shown in Fig. 9, the VG-LNA achieves continuous gain adjustment range of nearly 14.5 dB from 6.6 to 21.1 dB when VC is varied from +0.6 to +1.0 VDC in 0.05-V steps. Figure 10 shows the noise figure for the VG-LNA when sweeping VC: the noise figure is varied from 6.5 to 3.0 dB when VC is varied from +0.6 to +1.0 VDC in 0.05-V steps.

Variable-Gain LNA Reaches 26 GHz, Fig. 9

Variable-Gain LNA Reaches 26 GHz, Fig. 10

In short, a VG-LNA for K-band applications has been presented. The designed VG-LNA is composed of a resistance feedback current reuse stage and three cascaded common-source stages, and is simulated based on TSMC’s 0.18-μm silicon CMOS process. By using a highpass combination of L and C circuit elements loaded on the output of each stage to provide parallel resonance, the VG-LNA consumes only 6.48 mW from a +1-VDC supply while attaining gain of 21.1 dB and minimum noise figure of 3 dB at 26 GHz. With a controlling voltage, the gain and noise figure can adjusted over reasonably wide ranges.


1. Y.-K. Hsieh, J.-L. Kuo, H. Wang, et al., “A 60 GHz Broadband Low-Noise Amplifier With Variable-Gain Control in 65 nm CMOS,” IEEE Microwave and Wireless Components Letters, Vol. 21, No. 11, 2011, pp. 610-612.

2. W.-C. Wang, Z.-D. Huang, G. Carchon, et al., “A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High- Q Above-IC Inductors,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 5, 2009, pp. 326-328.

3. S.-C. Shin, M.-D. Tsai, R.-C. Liu, et al. “A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 μm CMOS technology,” IEEE Microwave and Wireless Components Letters, Vol. 15, No. 7, 2005, pp. 448-450.

4. S.-H. Yen and Y.-S. Lin, “Ka-band low noise amplifier using standard 0.18 μm CMOS technology,” Electronics Letters, Vol. 42, No. 16, 2006, pp. 919-920.

5. F. Yu and C. Wang, “CMOS LNA Boosts 64 GHz,” Microwaves & RF, Vol. 50, No. 10, 2011, pp. 64-77.

6. C. Wang, J. Jin, and F. Yu, “A CMOS 2-11 GHz Continuous Variable Gain UWB LNA,” IETE Journal of Research, Vol. 56, No. 6, 2010, pp. 367-372.

7. Y. Kim and Y. Kwon, “A 60 GHz Cascode Variable-Gain Low-Noise Amplifier With Phase Compensation in a 0.13 μm CMOS Technology,” IEEE Microwave and Wireless Components Letters, Vol. 22, No. 7, 2012, pp. 372-374.

8. C. Wang, J. Jin, and F. Yu, “Low-Power TIA Tunes Gain At 2.4 GHz,” Microwaves & RF, Vol. 49, No. 5, 2010, pp. 78-86.

9. T. Taris, J.-B. Begueret, and Y. Deval, “A low voltage current reuse LNA in a 130-nm CMOS technology for UWB applications,” in Proceedings of the 37th European Microwave Conference, Munich, Germany, 2007, pp. 1105-1108.

10. C.-W. Kim, M.-S. Jung, and S.-G. Lee, “Ultra-wideband CMOS low noise amplifier,” Electronics Letters, Vol. 41, No. 7, 2005, pp. 384-385.

11. W. Luo, C. Wang, and S. Du, “Design of 2-12 GHz Ultra-wideband CMOS low noise amplifier (in Chinese),” Microelectronics, Vol. 49, No. 2, 2010, pp. 243-247.