How It Stacks Up
To demonstrate the effectiveness of the design approach, a 26-GHz VG-LNA was designed and fabricated using a standard 0.18-μm CMOS process from TSMC. The circuit draws only 6.48 mW from a +1-VDC supply. Results were obtained using the post-layout simulation features of the Advanced Design System simulation software from Agilent Technologies. Figures 6 and 7 show gain and noise figure, respectively, as functions of frequency. The small-signal gain has a peak value of 21.1 dB and the noise figure has a minimum value of 3.0 dB at 26 GHz. Figure 8 shows input and output return losses, with minimum input and output return-loss levels of 23.3 dB and 21.6 dB, respectively.
As Fig. 4 indicates, controlling the gate voltage VC for device MC in the first stage can provide controllable gain. As shown in Fig. 9, the VG-LNA achieves continuous gain adjustment range of nearly 14.5 dB from 6.6 to 21.1 dB when VC is varied from +0.6 to +1.0 VDC in 0.05-V steps. Figure 10 shows the noise figure for the VG-LNA when sweeping VC: the noise figure is varied from 6.5 to 3.0 dB when VC is varied from +0.6 to +1.0 VDC in 0.05-V steps.
In short, a VG-LNA for K-band applications has been presented. The designed VG-LNA is composed of a resistance feedback current reuse stage and three cascaded common-source stages, and is simulated based on TSMC’s 0.18-μm silicon CMOS process. By using a highpass combination of L and C circuit elements loaded on the output of each stage to provide parallel resonance, the VG-LNA consumes only 6.48 mW from a +1-VDC supply while attaining gain of 21.1 dB and minimum noise figure of 3 dB at 26 GHz. With a controlling voltage, the gain and noise figure can adjusted over reasonably wide ranges.
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