DDS Model Tunes Doppler Simulation

Figure 1 shows a third-order, hybrid-clock DDS model, with three cascaded DDS accumulators. The first-stage accumulator is running at a different accumulation clock rate than the other two accumulators. The three accumulators in this hybrid-clock model are defined as the acceleration DDS accumulator (DDS_A), the velocity DDS accumulator (DDS_V), and the phase DDS accumulator (DDS_R), respectively.

Parameters k₀ through k₃ are the initial accumulation parameters of each accumulator stage; parameters θ₀ through θ₂ are the outputs of each different accumulator stage; N₀ is the word length of parameter k₀; and c₁ through c₃ are the bits that must be truncated when adding the accumulator output to the initial accumulator parameter. Parameters clk₀ and clk₁ are clock signals driving the first and additional accumulator stages, respectively, as represented in Eq. 2.

In Eq. 2, the clock frequency division coefficient, W ≥ 1, is an integer, so that the clock rate clk₀ will be at integral multiples of clk₁. If clk₀ < clk₁, the influence of the latter two accumulators on the first-stage accumulator can be converted and equivalent to a DDS model with same-clock accumulators. In the case of W = 1, the DDS model degenerates into the same-clock model presented in ref. 6.

Based on the model of Fig. 1, the output of each accumulator stage is derived when W is an unknown parameter. For DDS_A, when its initial value is k₂, the step value is k₃, and the number of the accumulated clock is m, so that its corresponding output sequence can be obtained according to Eq. 3.

Similarly, when the initial value for DDS_V is k₁, the step is θ₂(m - 1), and it is possible to calculate the corresponding output sequence by means of Eq. 4:

For the output sequence of DDS_R, while its initial value is k₀, the step is θ₁(n - 1), and the number of the accumulation clock is n; its output sequence can be expressed as Eq. 5. But since W is an unknown, the right-hand side of Eq. 5 cannot be directly expanded and summed:

Supposing that Y = [n/W], where the square brackets denote rounding the contained value to an integer, it is then possible to perform the summation of Eq. 6:

Incorporating Eq. 6 into Eq. 5 results in Eq. 7:

where:

t = the run duration;

v(t) = the real-time radial velocity;

s(t) = the real-time radial pseudorange amount;

R = the initial pseudorange amount;

v = the initial velocity;

a = the accelerated velocity; and

â = the amount of jerk.

The received signal Doppler frequency shift can be expressed as Eq. 9:

where:

f_d(t) = the Doppler frequency shift;

f_T = the nominal frequency of the simulated signal; and

c = the speed of light.

The signal phase can be expressed as Eq. 10:

If the signal phase is made discrete in Eq. 10, the sample clock is the working clock of the first-stage phase accumulator. When the clock cycle period is T_c = 1/f_c, the discrete signal phase sequence can be expressed by Eq. 11:

The final output phase of the hybrid-clock third-order DDS should precisely correspond to the simulated signal phase. To obtain initial accumulation parameters k₀ through k₃), it can be presumed that the output phase of the third-order DDS satisfies Eq. 12 at n = 0, W, 2W…iW for I ∈ Z+:

If Eq. 12 is the constraint condition, and N₀ and c₀ through c₃ are treated as known parameters, the values of k₀ through k₃ in Eq. 7 can be obtained. In the case where n = 0, W, 2W, 3W, from Eq. 12, Eq. 13 can be obtained:

A set of solutions from Eq. 13 can be obtained resulting in Eq. 14:

To prove that Eq. 14 satisfies Eq. 12 at any i ∈ Z+, mathematical induction is applied, with the following steps. For step 1, because Eq. 14 satisfies Eq. 12 when i = 0, 1, 2, and 3, it will satisfy the first step of the mathematical inductor. For step 2, supposing that Eq. 14 satisfies Eq. 12 when i = j, then when i = j + 1, it will yield Eq. 15:

Introducing Eq. 14 into Eq. 15 yields Eq. 16:

Similarly, the difference between p(jW) and p[(j + 1)W] can be expressed as Eq. 17:

Equation 18 can be obtained from Eqs. 16 and 17:

From Eq. 18, it is clear that Eq. 14 satisfies Eq. 12 when i = j + 1, which guarantees the validity of Eq. 14 for all i ∈ Z+ satisfying Eq. 12.

Compared with the results of ref. 6, the calculation results of same-clock condition is the case of W = 1 in Eq. 14. When W > 1, within each clk1 clock cycle period, the third-order DDS runs like a first-order DDS. Therefore, the hybrid-clock third-order DDS will generate larger pseudorange error as a same-clock DDS while running with the initial accumulation parameters calculated based on Eq. 14. Ignoring word-length quantization errors, this error can be expressed as Eq. 19:

Analysis of Eq. 19 is relatively complex, so the simulation method can be used to analyze the error. In case of f_c = 100 MHz and W ≤ 50, and assuming the conditions of Eq. 2 are met, the third-order DDS output pseudorange errors under the high-dynamic-range conditions represented by v = 1000 m/s; a = 1000 m/s², and â = 1000 m/s³ will be simulated. For a third-order DDS simulation run time of 10 ms, the maximum pseudorange errors for different W values are shown in Fig. 2. As W increases, the maximum pseudorange error caused by the hybrid clock increases correspondingly. In the case of W ≤ 10, the maximum pseudorange error is smaller than 10^-10 m. 

If f_c/W is large enough, the influence of the initial accumulation parameters on the Doppler frequency shift simulation errors under hybrid clock conditions can be ignored. With currently available FPGA-based DDS instruments, such a conditions can easily be satisfied.

Doppler simulation errors for the hybrid-clock third-order DDS can be mainly attributed to the quantization error of the word length at each stage. To achieve the required resolution for an accurate simulation, the word length of each accumulator stage must be designed. For this analysis, suppose that ΔR, Δv, Δa, and Δâ are the resolution of the pseudorange, the velocity, the acceleration, and the jerk amount, respectively. Fr the case of k_i = 1, the corresponding parameter should be smaller than the resolution. The word length obtained from Eq. 14 can be expressed in terms of Eq. 20:

The square brackets in Eq. 20 represent rounding to an integer value. It should be evident from Eq. 20 that the word length parameters for all three accumulators are N₀ + c₁, N₀ + c₁ + C₂, and N₀ + c₁ + c₂ + c₃, respectively. In addition, all the word length parameters are restricted to the lower bounds; in order to increase simulation precision, the word length parameter must be increased appropriately.

When W = 1, Eq. 20 reverts to the results for a same-clock third-order DDS. Considering the initial accumulation parameter calculation expressions, it is clear that the same-clock third-order DDS simulation model can be unified with the hybrid-clock simulation model. Under the requirement of the same design resolution, the lower bound of word length calculated by Eq. 20 is associated with W. The results obtained when W > 1 is shorter than the one when W = 1. Therefore, the resource and static power consumption can be reduced.

During this simulation, the phase sequence of the DDS_R accumulator within each simulation interval is obtained; a direct phase modeling method was adopted to estimate the Doppler frequency shift produced.¹⁰ By adopting this method, the frequency estimation accuracy is no longer dominated by receiver Doppler measurement accuracy when the receiver is adopted for verification. The simulation results are shown in Fig. 4 and the corresponding Doppler frequency shift errors in Fig. 5.

To check the accuracy of the Doppler frequency-shift estimations during the simulation, the data sampling intervals in Figs. 4 and 5 were increased to 200 ms. As Fig. 5 shows, even under different jerk rates, the hybrid-clock third-order DDS can maintain high Doppler simulation accuracy, and the error is always less than 2 mHz. The table compares resource and power consumption results for cases of W = 1 and W = 10.

To compare the simulation results to an actual unit, the FPGA used for analysis in the table was a model XC6SLX150 from Xilinx, and the power consumption analysis was produced with the aid of the company’s XPower Analyzer. In the case of W > 1, the resource and power consumption of the third-order DDS are decreased compared to a situation using multiple similar clocks. For W = 10, the word length reduction of each of the latter two accumulators is only 3, so the reduction of the resource and static power consumption is not obvious. However, the accumulation clock rate of the last two DDS accumulator stages is reduced to 1/W of the same-clock condition, which results in a dynamic power consumption reduction of approximately 1/W.

This hybrid-clock third-order DDS model can be used under both same-clock and hybrid-clock DDS conditions. The simulation results for the BeiDou2 B1 carrier signal show that the signal Doppler simulation method achieves precision of 2 mHz. Compared with the same-clock condition, the third-order DDS under hybrid-clock conditions operates with less resource requirements and power consumption. This simulation approach provides a means of precisely simulating Doppler signals, and is particularly useful for modeling portable high-dynamic-range satellite navigation equipment.

Zhang Yin, Doctoral Candidate

Li-Cai-Hua, Assistant

Huang Yang-Bo, Assistant

Zhang Guo-Zhu, Associate Professor

College of Electronic Science and Engineering, National University of Defense Technology, Changsha 410073, People’s Republic of China