Variable-Gain LNA Reaches 26 GHz

Figure 1 shows the basic topology of an amplifier with resistive-feedback input stage. The design can be studied with the simplified model depicted in Fig. 2. In addition, gain (A), noise figure (NF), and input impedance (Z_in can be calculated using Eqs. 1, 2, and 3, respectively⁹:

|A_V| ≈ g_m x (R_F x R_L)      (1)

NF ≈ 1 + [(2/(3g_mR_S)] x [(1/R_S) + R_S/ R_F²] + [(2f²g_mR_S/3f²_Tmin + (R_S/R_F)     (2)

Z_in ≈ (R_F + R_L)/(1 + |A_V|)   (3)

where:

g_m = the transconductance of transistor M;

R_L = the load resistance; and

R_F = the feedback resistance.

The circuit is assumed to be connected to a source generator with source impedance, R_S, that is typically 50 Ω.

Resistive feedback can be implemented with a current-reuse technique, as depicted in Fig. 3(a).¹⁰ Stacking both NMOS and PMOS transistors, the overall equivalent transconductance is increased from g_m to g_mN + g_mP for the same bias current. Furthermore, removing load resistance R_L enables this configuration to maintain the transistors in the saturation region with a minimal supply voltage, and without design tradeoffs.^6,9 In the current reuse configuration of Fig. 3(a), Eqs. (1) through (3) are kept the same according to the equivalent values listed in the table.

In the present amplifier design, an NMOS transistor replaces the traditional feedback resistor as shown in Fig. 3(b). In an ideal amplifier, the feedback resistance and gain characteristics are almost equivalent. The resistance value of the NMOS transistor can be derived as⁶:

r_ds ≈ L/[KW(V_gs - V_T)]            (4)

where:

K = Boltmann’s constant;

W = the effective channel width;

L = the effective channel length; and

V_T = the threshold voltage.

Building Blocks

From Eq. 4, it can be seen that as V_C changes, V_gs will change, then resistance r_ds will also change. Therefore, the feedback resistance is variable, as is the gain.

Figure 4 shows a complete schematic diagram of the 26-GHz CMOS VG-LNA. The preamplifier is comprised of a T-section matching network and a resistive-feedback current-reuse stage. Based on the methodology in ref. 10, simultaneously input impedance and noise matching at a frequency of 26 GHz was achieved by selecting appropriate values for the passive circuit elements C₁, C₂, and L₁ and the size and bias of the input resistive-feedback current-reuse network. Figure 5 provides a small-signal equivalent circuit of the preamplifier. From Fig. 5, the input impedance of the small-signal equivalent circuit is given by¹¹:

Z_in = 1/sC₁ || 1/sC₂ + sL₁ + Z_in1             (5)

where:

Z_in1 = 1/[Z_d/( Z_d + R_F)] x [(g_mN + g_mP) + s(C_gsN + C_gsP)]              (6)

and

Z_d = the input impedance of the post-amplifier.

To achieve sufficient gain, the post-amplifier is comprised of three cascaded common-source stages and an output matching network. In the first stage, proper scaling of the transistor and gate inductance are used to shift optimum source impedance, Z_opt, to 50 Ω, which makes it easier to achieve low noise figure. The output of each stage is loaded with a bandpass (or a highpass) combination of L and C to provide parallel resonance and to increase gain at the 26-GHz center frequency. Inductor L₆, which is connected to the source of transistor M₃, improves the stability of the LNA. The DC block, about 60 fF at the output, was chosen for output matching. Since this small capacitance might be sensitive to process variations, it has been composed of two MIM capacitors in series so as to desensitize the output matching from processing variation. The component parameters are as follows:

L₁ = 414.8 pH;  

L₂ = 1 pH;

L₃ = 327.4 pH;

L₄ = 96.7 pH;

L₅ = 260.7 pH;

L₆ = 114.6 pH;

C₁ = 7.6 pF;

C₂ = 273.65 pF;

C₃ = 4 pF;

C₄ = 70 fF;

C₅ = 10 pF;

C₆ = 60 fF;

R₁ = kΩ;

R₂ = kΩ; and

R₃ = kΩ.

The bias conditions are V_dd = +1 VDC and V_gg = +0.7 VDC. The CMOS transistors used in these circuits have been demonstrated to have cutoff frequency, f_t, of around 50 GHz and maximum frequency of oscillation, f_max, of around 90 GHz. The excellent f_t and f_max performance levels mean that it should be possible to use this CMOS process for high-performance K-band LNAs.

How It Stacks Up

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To demonstrate the effectiveness of the design approach, a 26-GHz VG-LNA was designed and fabricated using a standard 0.18-μm CMOS process from TSMC. The circuit draws only 6.48 mW from a +1-VDC supply. Results were obtained using the post-layout simulation features of the Advanced Design System simulation software from Agilent Technologies. Figures 6 and 7 show gain and noise figure, respectively, as functions of frequency. The small-signal gain has a peak value of 21.1 dB and the noise figure has a minimum value of 3.0 dB at 26 GHz. Figure 8 shows input and output return losses, with minimum input and output return-loss levels of 23.3 dB and 21.6 dB, respectively.

As Fig. 4 indicates, controlling the gate voltage V_C for device M_C in the first stage can provide controllable gain. As shown in Fig. 9, the VG-LNA achieves continuous gain adjustment range of nearly 14.5 dB from 6.6 to 21.1 dB when V_C is varied from +0.6 to +1.0 VDC in 0.05-V steps. Figure 10 shows the noise figure for the VG-LNA when sweeping V_C: the noise figure is varied from 6.5 to 3.0 dB when V_C is varied from +0.6 to +1.0 VDC in 0.05-V steps.

In short, a VG-LNA for K-band applications has been presented. The designed VG-LNA is composed of a resistance feedback current reuse stage and three cascaded common-source stages, and is simulated based on TSMC’s 0.18-μm silicon CMOS process. By using a highpass combination of L and C circuit elements loaded on the output of each stage to provide parallel resonance, the VG-LNA consumes only 6.48 mW from a +1-VDC supply while attaining gain of 21.1 dB and minimum noise figure of 3 dB at 26 GHz. With a controlling voltage, the gain and noise figure can adjusted over reasonably wide ranges.

References

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2. W.-C. Wang, Z.-D. Huang, G. Carchon, et al., “A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High- Q Above-IC Inductors,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 5, 2009, pp. 326-328.

3. S.-C. Shin, M.-D. Tsai, R.-C. Liu, et al. “A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 μm CMOS technology,” IEEE Microwave and Wireless Components Letters, Vol. 15, No. 7, 2005, pp. 448-450.

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